Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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16.4.3.1.7. CCS Timeout

If the command expects a CCS from the card device (the ccs_expected bit is set to 1 in the cmd register), the command state machine waits for the CCS and remains in the wait CCS state. If the CE‑ATA card fails to send out the CCS, the host software must implement a timeout mechanism to free the command and data path. The controller does not implement a hardware timer; it is the responsibility of the host software to maintain a software timer.

In the event of a CCS timeout, the host must issue a CCSD command by setting the send_ccsd bit in the ctrl register. The controller command path state machine sends the CCSD command to the CE‑ATA card device and exits to an idle state. After sending the CCSD command, the host must also send an SD/SDIO STOP_TRANSMISSION command to the CE‑ATA card to abort the outstanding ATA command.