Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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16.4.3.1.3. Send Response to BIU

If the response_expected bit is set to 1 in the cmd register, the received response is sent to the BIU. Response register 0 (resp0) is updated for a short response, and the response register 3 (resp3), response register 2 (resp2), response register 1 (resp1), and resp0 registers are updated on a long response, after which the cmd bit is set to 1 in the rintsts register. If the response is for an AUTO_STOP command sent by the CIU, the response is written to the resp1 register, after which the auto command done bit (acd) is set to 1 in the rintsts register.

The command path verifies the contents of the card response.

Table 135.  Card Response Fields
Field Contents

Response transmission bit

0

Command index

Command index of the sent command

End bit

1

The command index is not checked for a 136‑bit response or if the check_response_crc bit in the cmd register is set to 0. For a 136‑bit response and reserved CRC 48‑bit responses, the command index is reserved, that is, 0b111111.