Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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3.5.3.2. Translation Match Process

The ARMv8-A architecture supports multiple mappings of the virtual address space, which are translated differently. The TLB entries store all the required context information to facilitate a match and avoid a TLB flush or a context or virtual machine switch.

Each TLB entry contains a virtual address, block size, physical address, and a set of memory properties that include the memory type and access permissions. Each entry is associated with a particular application space ID (ASID), or is global for all application spaces.

The TLB entry also contains a field to store the virtual memory ID (VMID) for accesses made from the non-secure EL0 and EL1. A memory space identifier in the TLB entry records whether the request occurred at the:

  • EL3, if EL3 is in the AArch64 execution state
  • Non-secure EL2 exception level
  • Secure and non-secure EL0 or EL1 and EL3, when EL3 is in AArch32 execution state
A TLB entry match occurs when:
  • The virtual address matches that of the requested address
  • The memory space matches the memory space state of the requests. The memory space can be one of four values:
    • Secure EL3, when EL3 is in the AArch64 execution state
    • Non-secure EL2
    • Secure EL0 or EL1, and EL3 when EL3 is in the AArch32 execution state
    • Non-secure EL0 or EL1
  • The ASID matches the current application space ID held in the CONTEXTIDR, TTBR0, or TTBR1 register or the entry is marked global.
  • The VMID matches the current VMID held in the VTTBR register.
Note: For a request originating from EL2 or AArch64 EL3, the ASID and VMID match are ignored.
Note: For a request not originating from non-secure EL0 or EL1, the VMID match is ignored.