Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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17.4.4. PHY Interface Options

The table below identifies the signals used for each PHY interface selected.
Table 167.  PHY Interface Options
Port Name MII 42 GMII42 RMII43 SGMII44
emac_phy_txd_o[7:0] Yes, [3:0] Yes, [7:0] Yes, [1:0] Yes, [7:0]
emac_phy_mac_speed_o 45 Yes Yes Yes Yes
emac_phy_txen_o Yes Yes Yes Yes
emac_phy_txer_o 45 No Yes No Yes, part of transmit code
emac_phy_rxdv_i Yes Yes Yes Yes, part of receive code
emac_phy_rxer_i 45 Yes Yes No Yes, part of receive code
emac_phy_rxd_i[7:0] Yes, [3:0] Yes, [7:0] Yes, [1:0] Yes, [7:0]
emac_phy_col_i 45 Yes Yes No No
emac_phy_crs_i 45 Yes Yes No No
emac_clk_rx_i Yes Yes Yes Yes
emac_clk_tx_i 45 Yes Yes No Yes
emac_phy_txclk_o No Yes No Yes
emac_rst_clk_tx_n_o 45 Yes Yes No No
emac_rst_clk_rx_n_o 45 Yes Yes No No
emac_gmii_mdc_o Yes Yes Yes Yes

emac_gmii_mdo_o,

emac_gmii_mdo_o_e,

emac_gmii_mdi_i 46

Yes Yes Yes Yes
emac_ptp_pps_o 47 Yes Yes No No
emac_ptp_aux_ts_trig_i 47 Yes Yes No No
42 Default HPS EMAC interface for export to FPGA.
43 This option requires the Intel FPGA MII to RMII Converter Core.
44 This option requires the Intel FPGA HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core
45 This signal is only available through the FPGA interface.
46 These three signals make up the MDIO output signal.
47 This is an optional signal.