Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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7.3.4. FPGA-to-HPS Restrictions

Intel® Agilex™ uses all of the signaling defined within the ARM® AMBA* AXI* and ACE-Lite* Protocol Specification, except for the AxDOMAIN signaling and AxBURST signaling.

Note: For all coherent and cache maintenance operations, the Arteris FlexNoC network-onchip (NoC) interconnect technology ignores the signaled shareability attribute, and the transactions are processed as accesses within the Inner Sharable domain. This means that AxDOMAIN must be Inner Sharable (‘b01) and cannot be Outer Sharable (‘b10). For more information about Inner Sharable verses Outer Sharable, refer to the ARM® AMBA AXI* and ACE-Lite Protocol Specification ( ARM® IHI 0022H.c).

The AxUSER bits are exposed to the AXI* or ACE-lite interface of the FPGA-to-HPS bridge, and the transaction is controlled by its AXI* master. The AXI* master in the FPGA can set the AxUSER bits to 0x04 or 0xE0 on a per transaction basis to send the transaction either to the CCU directly or the SDRAM directly.