Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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10.4.6.2. Double-Bit Error Interrupt

All double-bit errors generate interrupts and the error memory address is logged into the recent double-bit error (DERRADDRx) register.

The Interrupt Status (INTSTAT) register indicates if a double-bit error has occurred. The double-bit error interrupt generation cannot be disabled. The interrupt is de-asserted by writing to the double-bit error pending bit of the INTSTAT register.

Double-bit errors that occur during a read-modify-write cycle for a sub-word access are flagged in the MODSTAT register in addition to triggering an interrupt.

Note: Because the DMA has eight individual decoders for each byte lane of its byte-accessible memory, the DECODERSTAT register provides extra information to the INSTAT register that indicates which of the individual decoders is flagging a double-bit error. All other ECC RAMs supported only have one decoder.