Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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15.5.2.6.5. Other Supported Commands

MAP01 commands must read or write pages in the same sequence that the pipelined commands were issued to the NAND flash controller. If the host issues multiple pipeline commands, pages must be read or written in the order the pipeline commands were issued. It is not possible to read or write pages for a second pipeline command before completing the first pipeline command. If the pipeline sequence is broken by a MAP01 command, the pipe_cmd_err interrupt is issued, and the flash controller clears the pipeline command queue. The flash controller services the violating incoming MAP01 read or write request with a normal page read or write sequence.

For a multi‑plane device that supports multi‑plane programming, you must set the flag bit of the multiplane_operation register in the config group to 1. In this case, the data is interleaved into page‑size chunks to consecutive blocks.

A pipe_cpyback_cmd_comp interrupt is generated when the NAND flash controller has finished processing a pipeline command and has discarded that command from its queue. At this point of time, the host can send another pipeline command. A pipeline command is popped from the queue, and an interrupt is issued when the flash controller has started processing the last page of pipeline command. Hence, the pipe_cpyback_cmd_comp interrupt is issued prior to the last page load in the case of a pipeline read command and start of data transfer of the last page to be programmed, in the case of a pipeline write command.

An additional program_comp interrupt is generated when the last page program operation completes in the case of a pipeline write command.

If the device command set requires the NAND flash controller to issue a load command for the last page in the pipeline read command, a load_comp interrupt is generated after the last page load operation completes.

The pipeline commands sequence advanced commands in the device, such as cache and multi‑plane. When the NAND flash controller receives a multi‑page read or write pipeline command, it sequences commands sent to the device depending on settings in the following registers in the config group:

  • cache_read_enable
  • cache_write_enable
  • multiplane_operation

For a device that supports cache read sequences, the flag bit of the cache_read_enable register must be set to 1. The NAND flash controller sequences each multi‑page pipeline read command as a cache read sequence. For a device that supports cache program command sequences, cache_write_enable must be set. The flash controller sequences each multi‑page write pipeline command as a cache write sequence.

For a device that has multi‑planes and supports multi‑plane program commands, the NAND flash controller register multiplane_operation, in the config group, must be set. On receiving the multi‑page pipeline write command, the flash controller sequences the device with multi‑plane program commands and expects that the host transfers data to the flash controller in an even‑odd block increment addressing mode.