Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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9.3.1. Read and Write Double-Bit Bus Errors

The integrated ECC Controller provides ECC protection to the on-chip RAM. The ECC controller detects and corrects single-bit errors. Double-bit errors are detected, but not corrected.

There are two types of double-bit bus errors:
  • Read—Double-bit errors that occur during a read access from the slave interface are reported back on the slave interface using the read bus error.
  • Write—Double-bit errors that occur during a write access from the slave interface are reported back on the slave interface using the write bus error.

This error response is true only if the corresponding double-bit error generation is enabled in the CTRL register of the ECC controller.