Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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18.4. USB 2.0 ULPI PHY Signal Description

Table 193.  ULPI PHY Interface Signals (Routed to HPS I/O)

The ULPI PHY interface is synchronous to the ulpi_clk signal coming from the PHY.

Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
USB<1:0>_CLK 1 Input

ULPI Clock.

Receives the 60-MHz clock supplied by the high-speed ULPI PHY. All signals are synchronous to the positive edge of the clock.

1'b1 Pull-up
USB<1:0>_DIR 1 Input

ULPI Data Bus Control

1 - The PHY has data to transfer to the USB OTG controller.

0 - The PHY does not have data to transfer.

1'b1 Pull-up
USB<1:0>_NXT 1 Input

ULPI Next Data Control.

Indicates that the PHY has accepted the current byte from the USB OTG controller. When the PHY is transmitting, this signal indicates that a new byte is available for the controller.

1'b1 Pull-up
USB<1:0>_STP 1 Output

ULPI Stop Data Control.

The controller drives this signal high to indicate the end of its data stream. The controller can also drive this signal high to request data from the PHY.

USB<1:0>_DATA[7:0] 8 Bidirectional

Bidirectional data bus.

Driven low by the controller during idle.

Pull-up