Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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16.5.12.2. Boot Operation for eMMC Card Device

The following figure illustrates the steps to perform the boot process for eMMC card devices. The detailed steps are described following the flow chart.
Figure 59. Flow for eMMC Boot Operation
  1. The software driver performs the following checks:
    • If the eMMC card device supports boot operation (the BOOT_PARTITION_ENABLE bit is set to 1 in the EXT_CSD register of the eMMC card).
    • The BOOT_SIZE_MULT and BOOT_BUS_WIDTH values in the EXT_CSD register, to be used during the boot process.
  2. The software sets the following bits:
    • Sets masks for interrupts, by setting the appropriate bits to 0 in the intmask register.
    • Sets the global int_enable bit of the ctrl register to 1. Other bits in the ctrl register must be set to 0.
      Note: Intel recommends that you write 0xFFFFFFFF to the rintsts and idsts registers to clear any pending interrupts before setting the int_enable bit. For internal DMA controller mode, the software driver needs to unmask all the relevant fields in the idinten register.
  3. If the software driver needs to use the internal DMA controller to transfer the boot data received, it must perform the following steps:
    • Set up the descriptors as described in Internal DMA Controller Transmission Sequences and Internal DMA Controller Reception Sequences”.
    • Set the use_internal_dmac bit of the ctrl register to 1.
  4. Set the card device frequency to 400 kHz using the clkdiv registers. For more information, refer to Clock Setup.
  5. Set the data_timeout field of the tmout register equal to the card device total access time, NAC.
  6. Set the blksiz register to 0x200 (512 bytes).
  7. Set the bytcnt register to a multiple of 128 KB, as indicated by the BOOT_SIZE_MULT value in the card device.
  8. Set the rx_wmark field in the fifoth register. Typically, the threshold value can be set to 512, which is half the FIFO buffer depth.
  9. Set the following fields in the cmd register:
    • Initiate the command by setting start_cmd = 1
    • Enable boot (enable_boot) = 1
    • Expect boot acknowledge (expect_boot_ack):
      • If a start‑acknowledge pattern is expected from the card device, set expect_boot_ack to 1.
      • If a start‑acknowledge pattern is not expected from the card device, set expect_boot_ack to 0.
    • Card number (card_number) = 0
    • data_expected = 1
    • Reset the remainder of cmd register bits to 0
  10. If no start‑acknowledge pattern is expected from the card device (expect_boot_ack set to 0) proceed to step 12.
  11. This step handles the case where a start‑acknowledge pattern is expected (expect_boot_ack was set to 1 in step 9).
    1. If the Boot ACK Received interrupt is not received from the controller within 50 ms of initiating the command (step 9), the software driver must set the following cmd register fields:
      • start_cmd = 1
      • Disable boot (disable_boot)= 1
      • card_number = 0
      • All other fields = 0

      The controller generates a Command Done interrupt after deasserting the CMD pin of the card interface.

      If internal DMA controller mode is used for the boot process, the controller performs the following steps after the Boot ACK Received timeout:

      • The DMA descriptor is closed.
      • The ces bit in the idsts register is set, indicating the Boot ACK Received timeout.
      • The ri bit of the idsts register is not set.
    2. If the Boot ACK Received interrupt is received, the software driver must clear this interrupt by writing 1 to the ces bit in the idsts register.

      Within 0.95 seconds of the Boot ACK Received interrupt, the Boot Data Start interrupt must be received from the controller. If this does not occur, the software driver must write the following cmd register fields:

      • start_cmd = 1
      • disable_boot = 1
      • card_number = 0
      • All other fields = 0

      The controller generates a Command Done interrupt after deasserting the CMD pin of the card interface.

      If internal DMA controller mode is used for the boot process, the controller performs the following steps after the Boot ACK Received timeout:

      • The DMA descriptor is closed
      • The ces bit in the idsts register is set, indicating Boot Data Start timeout
      • The ri bit of the idsts register is not set
    3. If the Boot Data Start interrupt is received, it indicates that the boot data is being received from the card device. When the DMA engine is not in internal DMA controller mode, the software driver can then initiate a data read from the controller based on the rxdr interrupt bit in the rintsts register.

      In internal DMA controller mode, the DMA engine starts transferring the data from the FIFO buffer to the system memory as soon as the level set in the rx_wmark field of the fifoth register is reached.

      At the end of a successful boot data transfer from the card, the following interrupts are generated:

      • The cmd bit and dto bit in the rintsts register
      • The ri bit in the idsts register, in internal DMA controller mode only
    4. If an error occurs in the boot ACK pattern (0b010) or an EBE occurs:
      • The controller automatically aborts the boot process by pulling the CMD line high
      • The controller generates a Command Done interrupt
      • The controller does not generate a Boot ACK Received interrupt
      • The application aborts the boot transfer
    5. In internal DMA controller mode:
      • If the software driver creates more descriptors than required by the received boot data, the extra descriptors are not closed by the controller. Software cannot reuse the descriptors until they are closed.
      • If the software driver creates fewer descriptors than required by the received boot data, the controller generates a Descriptor Unavailable interrupt and does not transfer any further data to system memory.
    6. If NAC is violated between data block transfers, the DRTO interrupt is asserted. In addition, if there is an error associated with the start or end bit, the SBE or EBE interrupt is also generated.

    The boot operation for eMMC card devices is complete. Do not execute the remaining (step 12).

  12. This step handles the case where no start‑acknowledge pattern is expected (expect_boot_ack was set to 0 in step 9).
    1. If the Boot Data Start interrupt is not received from the controller within 1 second of initiating the command (step 9), the software driver must write the cmd register with the following fields:
      • start_cmd = 1
      • disable_boot = 1
      • card_number = 0
      • All other fields = 0

      The controller generates a Command Done interrupt after deasserting the CMD line of the card. In internal DMA controller mode, the descriptor is closed and the ces bit in the idsts register is set to 1, indicating a Boot Data Start timeout.

    2. If a Boot Data Start interrupt is received, it indicates that the boot data is being received from the card device. When the DMA engine is not in internal DMA controller mode, the software driver can then initiate a data read from the controller based on the rxdr interrupt bit in the rintsts register.

      In internal DMA controller mode, the DMA engine starts transferring the data from the FIFO buffer to the system memory as soon as the level specified in the rx_wmark field of the fifoth register is reached.

      At the end of a successful boot data transfer from the card, the following interrupts are generated:

      • The cmd bit and dto bit in the rintsts register
      • The ri bit in the idsts register, in internal DMA controller mode only
    3. In internal DMA controller mode:
      • If the software driver creates more descriptors than required by the received boot data, the extra descriptors are not closed by the controller.
      • If the software driver creates fewer descriptors than required by the received boot data, the controller generates a Descriptor Unavailable interrupt and does not transfer any further data to system memory.

    The boot operation for eMMC card devices is complete.