Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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2.2.3. Cache Coherency Unit

The cache coherency unit allows I/O masters to maintain one-way coherency with the Cortex® -A53 MPCore™ . It acts as an interconnect among the processor, FPGA-to-HPS bridge, system MMU, multiport front end (MPFE) subsystem and peripheral masters interfacing the system interconnect and supports weighted priority of memory accesses.
The CCU features include:
  • Coherency directory to track the state of the L2 and L1 caches in the ARM® Cortex*-A53 MPCore™
  • Snoop filter support for tracking coherent lines and sending coherency transaction requests, including cache maintenance operations
  • Support for distributed virtual memory (DVM) using the ARM® AXI Coherency Extensions (ACE) protocol. Distributed virtual memory broadcast messages are sent to the Cortex® -A53 MPCore™ and translation control unit (TCU) in the system memory management unit (SMMU)
  • Quality-of-service (QoS) support for transaction prioritization using a weight bandwidth allocation
  • Interconnect debug capability through master and slave bridge status registers
  • Interrupt support for CCU transaction and counter events