Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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2.2.5.1. HPS-FPGA Memory-Mapped Interfaces

The HPS-FPGA memory-mapped interfaces provide the major communication channels among the HPS, the FPGA fabric, and SDRAM. The HPS-FPGA memory-mapped interfaces include:

  • FPGA-to-HPS bridge—a high–performance bus with a configurable data width of 128, 256, or 512 bits, allowing the FPGA fabric to master transactions to the slaves in the HPS or access to SDRAM through the MPFE interconnect. This interface allows the FPGA fabric to have full visibility into the HPS address space. This interface supports single-direction I/O coherency with the HPS MPU.
  • HPS-to-FPGA bridge—a high–performance interface with a configurable data width of 32, 64, or 128 bits, allowing the HPS to master transactions to slaves in the FPGA fabric.
  • Lightweight HPS-to-FPGA bridge—an interface with a 32–bit fixed data width, allowing the HPS to master transactions to slaves in the FPGA fabric. This bridge is primarily used for control and status register accesses.