Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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5. System Memory Management Unit

The system memory management unit (SMMU) provides memory management services to system bus masters. The SMMU translates input addresses to output addresses based on address mapping and memory attribute information in the SMMU registers and translation tables. The SMMU also provides caching attributes for physical pages. A single translation control unit (TCU) manages distributed translation buffer units (TBUs) and performs page table walks (PTWs) on translation misses.

The SMMU conforms to the ARM® SMMU v2 Specification.

Table 44.  SMMU IP Description
Description Revision Number
ARM® CoreLink* MMU-500 r2p4