Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.6.1. MPFE Subsystem

The multiport front end (MPFE) subsystem connects the HPS to the hard memory controller adaptor (HMCA) that is located in the FPGA portion of the device. The MPFE subsystem includes an MPFE Interconnect, which is secured by firewalls. It supports AMBA* AXI* QoS for the FPGA fabric interfaces.

The MPFE Subsystem implements the following high-level features:

  • Support for double data rate 4 (DDR4) devices
  • Software-configurable priority scheduling per port
  • 8-bit Single Error Correction, Double Error Detection (SECDED) ECC with write-back, and error counters
  • Fully-programmable timing parameter support for all JEDEC®‑specified timing parameters
  • All ports support memory protection and mutual-exclusive accesses