Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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5.4.5. Translation Control Unit

The TCU cache consists of macro TLB, prefetch buffers, IPA to PA support and PTW caches.

The prefetch buffer fetches pages up to 16 KB in size. The prefetch buffer is a single four-way associative cache that you can enable or disable depending on the context.