Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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B.3. Quad SPI Flash Controller Block Diagram and System Integration

Figure 133. Quad SPI Flash Controller Block Diagram and System Integration

The quad SPI controller consists of the following blocks and interfaces:

  • Data slave controller - Interface and controller that provides the following functionality:
    • Performs data transfers to and from the interconnect
    • Validates incoming accesses
    • Performs byte or half-word reordering
    • Performs write protection
    • Forwards transfer requests to direct and indirect controller
  • Indirect access controller - provides higher-performance access to the flash memory through local buffering and software transfer requests
  • Direct access controller - provides memory-mapped slaves direct access to the flash memory
  • Software triggered instruction generator (STIG) - generates flash commands through the flash command register (flashcmd) and provides low-level access to flash memory
  • Flash command generator - generates flash command and address instructions based on instructions from the direct and indirect access controllers or the STIG
  • Register slave interface - Provides access to the control and status registers (CSRs)
  • SPI PHY - serially transfers data and commands to the external SPI flash devices