Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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2.2.10.1. EMACs

The three EMACs are based on the Synopsys®  DesignWare* 3504‑0 Universal 10/100/1000 Ethernet MAC. Each of the EMACs offers the following features:
  • IEEE 802.3-2008 compliant
  • Supports 10, 100, and 1000 Mbps standard
  • Supports full and half duplex modes
  • IEEE 1588-2002 and 2008 precision networked clock synchronization
  • IEEE 802.3-az, version D2.0 of Energy Efficient Ethernet (EEE)
  • Supports IEEE 802.1Q Virtual local area network (VLAN) tag detection for reception frames
  • VLAN insertion, replacement, or deletion
  • Supports a variety of flexible address filtering modes
  • Programmable frame length support for full jumbo frames up to 9000 Bytes
  • The Gigabit media independent interface/Media independent interface (GMII/MII) interface includes optional FIFO loopback to support debugging
  • Network statistics with RMON/MIB counters (RFC2819/RFC2665)
  • PHY interface support for Reduced Gigabit Media Independent Interface (RGMII) and Reduced Media Independent Interface (RMII) on HPS I/O pins
  • PHY interface support for GMII and MII on FPGA I/O pins:
    • Additional PHY interface support on FPGA I/O pins using adapter logic in the FPGA fabric to adapt the GMII/MII interface from the HPS to interfaces such as Serial Gigabit Media Independent Interface (SGMII) or RMII
    Note: The Intel® Agilex™ SoC device does not support adapting the HPS EMAC signals to RGMII using FPGA I/O pins.
  • PHY Management control through Management data input/output (MDIO) interface or I2C interface
  • Integrated DMA controller