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Ixiasoft
Visible to Intel only — GUID: yku1697542908888
Ixiasoft
4.1. Implement Required Clocking
This section describes the required clock connections and clock signals for various GTS Ethernet Intel® FPGA Hard IP core variations.
The following image shows the clock connection for Synchronous Adapter Modes.
- i_clk_ref PMA reference clock
- i_clk_sys datapath clock.
You can drive the PMA reference clock, i_clk_ref, from either local or regional clock pins. The local reference clock pin is bidirectional, except when there is a single GTS transceiver bank on an FPGA side, where it functions solely as an input reference clock pin. You can configure this bidirectional pin as an output for the Clock Data Recovery (CDR) recovered clock o_cdr_divclk from any of the four channels within the GTS transceiver bank. The device with a single GTS transceiver bank has a dedicated output pin for the CDR recovered clock. For more information about the GTS System PLL Intel® FPGA IP, refer to the GTS Transceiver PHY User Guide.
The output of the GTS System PLL Clocks Intel® FPGA IP drives the i_clk_sys datapath clock. The GTS System PLL Intel® FPGA IP sources its input reference clock i_refclk from either a local, regional, or HVIO reference clock pin.
Additionally, the GTS Ethernet Intel® FPGA Hard IP receives its i_clk_sys clock from the IP PLL in the HVIO bank.
The following table describes the input and output clocks with required clock frequencies, and the clock-related status signals.
Name | Description |
---|---|
Clock Inputs | |
i_clk_tx | TX datapath clock Drives the active TX Interface for the channel. Clock source:
Clock frequencies:
|
i_clk_rx | RX datapath clock Drives the active RX Interface for the channel.
Clock source:
Clock frequencies:
|
i_clk_sys | Ethernet system clock
Ethernet System Clock from GTS System PLL Clocks Intel® FPGA IP .
Note: The i_clk_sys is a virtual signal. In simulation, the signal appears as 0.
|
i_clk_ref_p |
PMA Reference Clock
|
i_reconfig_clk | Avalon memory-mapped interface reconfiguration clock Avalon® memory-mapped interface uses this clock to access control status registers (CSRs). This clock supports 100 to 125 MHz frequency. |
i_clk_pll | PTP-related datapath clock
This clock drives the i_clk_tx and i_clk_rx when both, Enable IEEE 1588 PTP and Enable asynchronous adapter clocks parameters, are enabled.
Note: When Enable IEEE 1588 PTP parameter is disabled, tie this port to 1'b0.
|
i_pma_cu_clk | PMA Control Unit Clock Connect this clock to o_pma_cu_clk output of the GTS Reset Sequencer Intel® FPGA IP . Refer to input and output signals of Connect the GTS Reset Sequencer Intel FPGA IP for more details. |
i_pma_cu_clk | PMA Control Unit Clock Connect this clock to o_pma_cu_clk output of the GTS Reset Sequencer Intel® FPGA IP . Refer to input and output signals of Connect the GTS Reset Sequencer Intel FPGA IP for more details. |
Clock Outputs | |
o_clk_pll | System PLL clock Clock derived from the GTS Ethernet Intel® FPGA Hard IP . The frequency is the system PLL frequency divided by 2 (e.g., 806 MHz system PLL would result in a 403 MHz o_clk_pll)
|
o_clk_tx_div | Clock derived from TX PLL. Its frequency is the data rate divided by 66.
|
o_clk_rec_div64 | This recovered clock is derived from the CDR. Its frequency is the data rate divided by 64.
Note: The frequency is calculated as o_clk_tx_div.
|
o_clk_rec_div | This recovered clock is derived from the CDR. Its frequency is the data rate divided by 66.
Note: The frequency is calculated as o_clk_tx_div.
|
o_cdr_divclk | Dedicated CDR divided clock output from PMA over the Local Reference Clock pins or dedicated CDR clock output pins. Refer to Figure 12 This clock is available when Enabled Dedicated CDR Clock Output is enabled in the IP parameter editor. |
Name | Description |
---|---|
i_syspll_lock | Indicates that the Sys PLL IP is locked. |
o_cdr_lock | This signal indicates that the recovered clocks are locked to data. Do not use o_clk_rec_div64 or o_clk_rec_div until o_cdr_lock is high. |
o_sys_pll_locked | Indicates o_clk_pll is stable. |
o_tx_pll_locked | TX SERDES PLLs are locked. Do not use o_clk_tx_div until o_tx_pll_locked is high. |
Section Content
Implement MAC Synchronous Clock Connections to Single Instance
Implement MAC Synchronous Clock Connections to Multiple Instances
Implement Clock Connections to MAC Asynchronous Operation
Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
Implement Clock Connections in PTP-Based Design