GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public

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4.6.1. Connect the FlexE and OTN Mode TX Interface

The GTS Ethernet Intel® FPGA Hard IP TX client interface in FlexE and OTN variations is a PCS66 interface.

Connect the TX PCS66 interface, sink, to a source complaint to the PCS66 interface specification. The source can send PCS66 blocks directly to the TX PCS, bypassing the TX MAC.

Connect to the interface as described in the following table.

Table 37.  PCS66 TX Interface SignalsAll interface signals are clocked by i_clk_tx signal. The signal names are the standard PCS66 interface.
Signal Name Width Description
i_tx_pcs66_d[65:0] 66 bits (10GE/25GE)

Drive this data bus with 66-bit data blocks from a source. The two least significant bits are the header synch bits.

  • In FlexE mode, the TX PCS scrambles the 66-bit data block and stripes the data blocks across the transceiver channels.
  • In OTN mode, the TX PCS bit-interleaves the 66-bit data block and stripes it across the transceiver channels.
i_tx_pcs66_valid 1 bit

Drive this signal high to qualify the 66-bit data block on the i_tx_pcs66_d input data bus.

o_tx_pcs66_ready 1 bit

When this signal is asserted, drive valid 66-bit data blocks. When this signal is deasserted or removed, do not drive valid data blocks. See this waveform Figure 42 for an example.

i_tx_pcs66_am 1 bit for each channel
In FlexE mode, assert this signal so have the TX PCS insert alignment markers, ignoring the data on the i_tx_pcs66_d.
  • In OTN mode, RS-FEC must be aware of the alignment marker location.
  • In OTN mode, tie this signal low.
  • In FlexE mode the TX encoder in the PCS is bypassed.
  • In OTN mode, both the TX encoder and the scrambler are bypassed.

The following waveform shows how to send the 66b blocks directly to the TX PCS in FlexE and OTN mode using the PCS66 TX Interface.

Figure 42. Transmitting Data on the PCS66 TX Interface
Drive i_tx_pcs66_valid according to the following:
  • Assert only when o_tx_pcs66_ready is asserted and deassert only o_tx_pcs66_ready is deasserted.
  • Hold the value on i_tx_pcs66_d when o_tx_pcs66_valid is deasserted.

The byte order for the PCS66 mode TX interface is the same as the TX MII PCS interface. Bytes are transmitted from least to most significant byte. The first byte to be transmitted is i_tx_pcs66_d[65:0].

The bit order for the PCS66 mode TX interface is the same as the TX PCS interface. Bytes are transmitted from least to most significant bit. The first bit to be transmitted from the interface is i_tx_pcs66_d[0].