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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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10.3.1. Simulation Testbench Flow
The following steps show the simulation testbench flow:
- Assert global reset (i_rst_n) to reset each GTS Ethernet Intel® FPGA IP and GTS Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP.
- Wait until configuration settings load
- Wait until reset acknowledgment. The o_rst_ack_n signal goes low..
- Deasserts the global resets, i_rst_n and i_reconfig_rst.
- Wait until the auto-negotiation is complete, and then begin the data mode.
- Wait until link training is complete.
- Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
- Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
- Instruct packet client to transmit data. Write hw_pc_ctrl[0]=1'b1 to start the packet generator.
- Read TX packet data information from 0x20 - 0x34 registers. Read registers in a sequential order.
- Read RX packet data information from 0x38 - 0x4C registers. Read registers in a sequential order.
- Compare the counters to ensure 16 packets were sent and received.
- Instruct packet client to stop data transmission. Write hw_pc_ctrl[2:0]=3'b100 to stop the packet generator. Clear counters.
- Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers.
- 0x104: Scratch register
- 0x108: IP soft reset register
- 0x014: Lower 32 bits of TX MAC Source address Register
- 0x018: Upper 16 bits of TX MAC Source address Register
- 0x01C: Max RX frame size register
- Perform Avalon® memory-mapped interface 2 test to read and write operation transceiver registers.