GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)

When you enable the Synchronous Ethernet (Sync-E) mode, two or more channels can share the off-chip cleanup PLL clock output. The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommendations, requires that the TX clock be filtered to maintain synchronization with the RX reference clock through a sequence of nodes. You must drive the transceiver reference clocks with a filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain synchronized. In this scenario, a design component outside the IP performs the filtering.

Figure 17. Clock Connection of Sync-E Clock Through CDR Clock Out Pin

The diagram above shows the clocking requirement to enable SyncE operation. The recovered clock outputs o_clk_rec_div or o_clk_rec_div64 or o_cdr_divclk from the GTS Ethernet Intel® FPGA Hard IP are connected to the off-chip cleanup PLL using the REFCLK_GTS pin. The dedicated clock output (o_cdr_divclk) from the PMA can be driven to a local reference clock pin or dedicated clock output pins if the device has single transceiver bank, whereas the clocks o_clk_rec_div64 and o_clk_rec_div are available at GPIO pins.

For more information about the supported pins, refer to Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs.

Two or more channels share the clock output of an Off-chip Cleanup PLL that meets the specification for a SyncE link. The FPGA provides a primary SyncE clock and a backup SyncE clock to the cleanup PLL. The primary and backup cleanup clocks come from recovered clock output pins from a pair of channels that are both connected to remote stations connected to the same SyncE network, with the transceiver reference clock sourced from the output of the cleanup PLL. Refer to the following figure to enable the Sync-E option:

Figure 18. Enable Sync-E option in the IP Parameter Editor

The output frequency is equal to the nominal incoming i_clk_ref divided by any predivider on the RX path. The following table shows the recovered clock frequencies with respect to input reference clock.

Table 20.  Recovered Clock Frequency
Data Rate Input Refclk (MHz) N Divider Output Recovered Clk (MHz)
10GE 156.25 1 156.25
312.5 2 156.25
322.265625 3 107.421875
25GE 156.25 4 39.0625
312.5 8 39.0625
322.265625 3 107.421875
Note: If the EHIP System clock is derived from a different reference clock than the transceiver, then set the IP to "System PLL" in “Custom Cadence” mode option to match the PPM difference between the clocks. For Sync-E applications, the local oscillator must match the recovered clock within +/-4.6ppm.