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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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B.1. Ethernet Avalon® Memory-Mapped Interface Address Space
The Reconfiguration Ethernet interface (reconfig_eth) provides access to the Ethernet Hard IP Avalon® Memory-Mapped Interface space for the local Ethernet Hard IP, including MAC, PCS, and FEC interface, the interface to the PMA, as well as soft CSRs implemented in the FPGA fabric. All addresses are byte-based address even though the register description specifies 32 bit boundary. The GTS Ethernet Intel® FPGA Hard IP register addresses are byte-addressable.
Refer to the GTS Ethernet Intel® FPGA Hard IP Register Map to view the register map and registers description.
Address Range | Register Type |
---|---|
0x0000_0100 - 0x0000_0FFC | Soft Control Status Registers (Soft CSRs) |
0x0004_0000 – 0x0004_0F7C | PTP Registers |
0x0010_0000 - 0x0010_0054 | Packet Client Registers |
0x0005_0000 – 0x0005_0F7C | Media Access Control (MAC) |
0x0006_0000 – 0x0006_01FC | Physical Coding Sublayer (PCS) |
0x0007_0000 – 0x0007_1FFC | Forward Error Code (FEC) |
0x0008_0000 – 0x0008_1FFC | PMA Interface |
0x0009_0000 – 0x000C_FFFC | Physical Media Attachment (PMA) |
Attention: GTS Ethernet Intel® FPGA Hard IP enters a hang state when reserved AVMM register space in PCS/Ethernet Hard IP is accessed. It is not recommended to access the IP's invalid or reserved Configuration Status Register. Access only the defined address range.
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