GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

B.1. Ethernet Avalon® Memory-Mapped Interface Address Space

The Reconfiguration Ethernet interface (reconfig_eth) provides access to the Ethernet Hard IP Avalon® Memory-Mapped Interface space for the local Ethernet Hard IP, including MAC, PCS, and FEC interface, the interface to the PMA, as well as soft CSRs implemented in the FPGA fabric. All addresses are byte-based address even though the register description specifies 32 bit boundary. The GTS Ethernet Intel® FPGA Hard IP register addresses are byte-addressable.

Refer to the GTS Ethernet Intel® FPGA Hard IP Register Map to view the register map and registers description.

Table 65.  Reconfiguration Ethernet Avalon® Memory-Mapped Interface BASE Address RangesThe description for the reconfiguration ethernet interface is provided in IP-XACT format upon IP core generation. Below table displays all eth_reconfig base addresses.
Address Range Register Type
0x0000_0100 - 0x0000_0FFC Soft Control Status Registers (Soft CSRs)
0x0004_0000 – 0x0004_0F7C PTP Registers
0x0010_0000 - 0x0010_0054 Packet Client Registers
0x0005_0000 – 0x0005_0F7C Media Access Control (MAC)
0x0006_0000 – 0x0006_01FC Physical Coding Sublayer (PCS)
0x0007_0000 – 0x0007_1FFC Forward Error Code (FEC)
0x0008_0000 – 0x0008_1FFC PMA Interface
0x0009_0000 – 0x000C_FFFC Physical Media Attachment (PMA)
Attention: GTS Ethernet Intel® FPGA Hard IP enters a hang state when reserved AVMM register space in PCS/Ethernet Hard IP is accessed. It is not recommended to access the IP's invalid or reserved Configuration Status Register. Access only the defined address range.