GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public

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5.4. Compile the Design Example in Hardware

To compile the hardware design example and configure it on your Agilex™ 5 device, follow these steps:
  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, navigate to the Quartus® Prime project directory <design_example_dir>/hardware_test_design/intel_eth_gts.qpf.
  3. On the Processing menu, click Start Compilation.
  4. Confirm successful compilation by verifying that the IP generates the bitstream file (.sof) and meets the timing requirements.
  5. After successful compilation, a .sof file is available in <design_example_directory>/hardware_test_design/output_files directory.