GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

4.9. Connect the Auto-Negotiation and Link Training

The following four components are required to create an Ethernet Port with AN/LT IP enabled.
  • The central component is the Ethernet Hard IP.
  • The second component is the AN/LT IP which drives the AN/LT process.
  • The third component is a System PLL IP which generates a system clock for the Ethernet IP.
  • The fourth component is the Reset Sequencer IP which is used to stagger resets to prevent power-droop glitches.

The following diagram shows the interconnection signals required for Ethernet with AN/LT. Once the four required components are generated, connect them as shown in the diagram.

Figure 53. Auto-Negotiation and Link Training for GTS Ethernet Intel® FPGA Hard IP
Table 46.  Clock and Reset Ports
Name Description
i_clk Clock source with 100 MHz frequency. When AN/LT is enabled, drive the i_clk at 1 GHz for faster simulation times.
i_reset Active high reset, synchronous to i_clk clock.
Table 47.  User Avalon® Memory-Mapped Interface PortsThe following interface signals are clocked by the i_clk_signal and are used for read/write access to the AN/LT IP registers.
Name Width Description
i_kr_reconfig_addr[11:0] 12 Address bus for auto-negotiation and link training control and status registers (AN/LT CSRs).
  • Bits [11:8]: Port number
  • [7:0]: CSR space for each port
i_kr_reconfig_read 1 Read enable for AN/LT CSRs.
i_kr_reconfig_write 1 Write enable for AN/LT CSRs.
i_kr_reconfig_byte_en[3:0] 4 AN/LT byte enable signal for writing data.
i_kr_reconfig_writedata[31:0] 32 Write data for AN/LT CSRs.
o_kr_reconfig_readdata[31:0] 32 Read data from AN/LT CSRs.
o_kr_reconfig_readdata_valid 1 Valid signal for AN/LT CSRs read data. When asserted, the register is valid.
o_kr_reconfig_waitrequest 1 Indicates that the Avalon® memory-mapped interface is busy. The read or write cycle is only complete when this signal goes low.
Table 48.  Local Avalon Memory-Mapped Interface Ports to Connect to Base Ethernet IP Transceiver ChannelsThe i_clk_signal clocks the interface signals below, which connect each set of Avalon Memory-Mapped signals to a transceiver channel.

<prt_num> goes from 0 to 15 based on the number of ports selected.

Name Width Description
kr_xcvr_0_reconfig_addr[17:0] 18 Address for transceiver
kr_ xcvr_0_reconfig_read 1 Read enable for transceiver registers.
kr_ xcvr_0_reconfig_write 1 Write enable for transceiver registers.
kr_xcvr_0_reconfig_byte_en[3:0] 4 Data byte enable for transceiver registers.
kr_xcvr_0_reconfig_writedata[31:0] 32 Write data for transceiver registers.
xcvr_kr_0_reconfig_readdata[31:0] 32 Read data for transceiver registers.
xcvr_kr_0_reconfig_readdata_valid 1 Valid signal for AN/LT CSRs read data. When asserted, the register is valid.
xcvr_kr_0_reconfig_waitrequest 1 Indicates that the local Avalon® memory-mapped interface is busy. The read or write cycle is only complete when this signal goes low.
Table 49.  KR status and Control Signals to connect to Base IP Transceiver ChannelsThe table below illustrates the connections for each set of kr_stat and kr_ctrl signals to the Ethernet SIP.
Name Width Description
kr_ctrl_xcvr_<prt_num>[0] 1 TX/RX lane desired signal controls the SRC (Soft Reset Controller) state when the kr_mode signal is set to active.
kr_ctrl_xcvr_<prt_num>[1] 1 Kr_mode signal that allows KR IP to set the TX/RX SRC desired lane states.
kr_ctrl_xcvr_<prt_num>[2] 1 The Kr_fec_mode signal indicates that the FEC mode is enabled.
kr_ctrl_xcvr_<prt_num>[3] 1 The TX/RX freeze SRC signal becomes active when the kr_mode signal is set.
kr_ctrl_xcvr_<prt_num>[7:4] 4 Reserved.
kr_stat_xcvr_<prt_num>[0] 1 Indicates KR reset ACK (acknowledgment) signal is set.
kr_stat_xcvr_<prt_num>[1] 1 Indicates that the PCS is fully aligned.
kr_stat_xcvr_<prt_num>[2] 1 Indicates that the HI BER (High Bit Error Rate) signal is set.
kr_stat_xcvr_<prt_num>[3] 1 Indicates that both TX/RX Freeze SRC ACK signals are set.
kr_stat_xcvr_<prt_num>[7:4] 4 Reserved.