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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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B.2. Packet Client Registers
You can customize the GTS Ethernet Intel® FPGA Hard IP hardware design example by programming the packet client registers for IP variants. These registers are not included in the GTS Ethernet Intel® FPGA Hard IP Register Map.
To access the packet client registers, the address value is calculated using both the base and offset address. For example, to access hw_test_rom_addr register, add offset address 0x08 to the packet client register base address 0x100000, which results in 0x100008.
Address | Name | Bit Offset | Default Value | Access | Description |
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0x00 | hw_pc_ctrl | 0 | 1'b0 | RW | Start and stop of the TX packet generation.
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2 | 1'b0 | RW | Packet transmission mode.
When you switch from continuous to one time mode, you must set hw_pc_ctrl[0] to 1 to ensure the pending packet transmission is completed. |
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4 | 1'b0 | RW | Packet client loopback.
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6 | 1'b0 | RW | The snapshot status for all statistics counter registers.
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7 | 1'b0 | RW | The clear status of the snapshot registers.
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8 | 1'b0 | RW | The EOP of TX packet and clears the counters. | ||
0x0C | Loopback_FIFO_status | [0] | 0 | RW | Loopback FIFO write full error |
[1] | 0 | RW | Loopback FIFO read empty error | ||
[15:2] | 14'h0000 | RW | Reserved. Default 0s | ||
0x1C | cfg_rom_pkt_gap | [4:0] | 0 | RW | Gap insertion between the packets. avst: min gap = 0; max gap = 31 |
[31:5] | 0 | RW | Reserved. Default 0s. | ||
0x04 | hw_test_loop_cnt | [15:0] | 16'd1 | RW | Indicates the number of times the ROM packet data are sent. |
0x08 | hw_test_rom_addr | [15:0] | 16'd0 | RW | ROM packet data start address |
[31:16] | 16'd0 | RW | ROM packet data end address | ||
0x10 | Latency Reg | [7:0] | 8'h00 | RO | Latency Value in terms of o_clk_pll |
[30:8] | 23'd0 | RO | Reserved | ||
[31] | 0 | RW | Latency enable bit (self- clearing) | ||
0x14 | cfg_rom_da_addr | [31:0] | 0 | RW | Destination address LSB 32 bits |
0x18 | Cfg_rom_da_adr_h | [15:0] | 0 | RW | Destination address LSB 16 bits |
[16] | 0 | RW | 16th bit = 1/0 to enable/disable DA insertion | ||
[31:17] | 0 | RW | Reserved. Default 0s | ||
0x20 | stat_tx_sop_cnt_lsb | [31:0] | 32'b0 | RO | Lower 32-bits of the TX start-of-packet (SOP) counter |
0x24 | stat_tx_sop_cnt_msb | [31:0] | 32'b0 | RO | Upper 32-bits of the TX start-of-packet (SOP) counter |
0x28 | stat_tx_eop_cnt_lsb | [31:0] | 32'b0 | RO | Lower 32-bits of the TX end-of-packet (EOP) counter |
0x2C | stat_tx_eop_cnt_msb | [31:0] | 32'b0 | RO | Upper 32-bits of the TX end-of-packet (EOP) counter |
0x30 | stat_tx_err_cnt_lsb | [31:0] | 32'b0 | RO | Lower 32-bits of the TX error counter |
0x34 | stat_tx_err_cnt_msb | [31:0] | 32'b0 | RO | Upper 32-bits of the TX error counter |
0x38 | stat_rx_sop_cnt_lsb | [31:0] | 32'b0 | RO | Lower 32-bits of the RX start-of-packet (SOP) counter |
0x3C | stat_rx_sop_cnt_msb | [31:0] | 32'b0 | RO | Upper 32-bits of the RX start-of-packet (SOP) counter |
0x40 | stat_rx_eop_cnt_lsb | [31:0] | 32'b0 | RO | Lower 32-bits of the RX end-of-packet (EOP) counter |
0x44 | stat_rx_eop_cnt_msb | [31:0] | 32'b0 | RO | Upper 32-bits of the RX end-of-packet (EOP) counter |
0x48 | stat_rx_err_cnt_lsb | [31:0] | 32'b0 | RO | Lower 32-bits of the RX error counter |
0x4C | stat_rx_err_cnt_msb | [31:0] | 32'b0 | RO | Upper 32-bits of the RX error counter |
Address | Name | Bit Offset | Default Value | Access | Description |
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0x10 | cfg_start_pkt_gen | 0 | 1'b0 | RW | Start and stop TX packet generator.
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0x58 | cfg_clear_counters | 0 | 1'b0 | RW | When set, clears packet generator counters. |
0x18 | stat_tx_sop_cnt | [31:0] | 32'b0 | RO | Lower 32-bits of the TX start-of-packet (SOP) counter |
0x1C | stat_tx_sop_cnt | [31:0] | 32'b0 | RO | Upper 32-bits of the TX start-of packet (SOP) counter |
0x20 | stat_tx_eop_cnt | [31:0] | 32'b0 | RO | Lower 32-bits of the TX end-of-packet (EOP) counter |
0x24 | stat_tx_eop_cnt | [31:0] | 32'b0 | RO | Upper 32-bits of the TX end-of-packet (EOP) counter |
0x30 | stat_rx_sop_cnt | [31:0] | 32'b0 | RO | Lower 32-bits of the RX start-of-packet (SOP) counter |
0x34 | stat_rx_sop_cnt | [31:0] | 32'b0 | RO | Upper 32-bits of the RX start-of-packet (SOP) counter |
0x38 | stat_rx_eop_cnt | [31:0] | 32'b0 | RO | Lower 32-bits of the RX end-of-packet (EOP) counter |
0x3C | stat_rx_eop_cnt | [31:0] | 32'b0 | RO | Upper 32-bits of the RX end-of-packet (EOP) counter |
0x50 | stat_rx_err_cnt | [31:0] | 32'b0 | RO | Lower 32-bits of the RX error status |
0x54 | stat_rx_err_cnt | [31:0] | 32'b0 | RO | Upper 32-bits of the RX error status |