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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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4.8. Connect the Ethernet Hard IP Reconfiguration Interface
Connect the Ethernet Reconfiguration Interface, an Avalon® MM slave, to an Avalon® MM master, to enable the master to read the control and status address space of the GTS Ethernet Intel® FPGA Hard IP.
Figure 52. Signals of the Ethernet Hard IP Reconfiguration Interface
The following diagram shows how to read and write data using the Ethernet reconfiguration Avalon® memory-mapped interface.
Figure 53. Ethernet Hard IP Reconfiguration Interface Waveform Signals
Connect the interface signals according to the rules and description provided in the following table. All of these signals are synchronous to the i_reconfig_clk.
Port Name | Width | Description |
---|---|---|
i_reconfig_eth_addr | 18 bits | Byte address bus for Ethernet control and status registers. |
i_reconfig_eth_byteenable | 4 bits | Byte enable for Ethernet read and write request signals. |
i_reconfig_eth_read | 1 bit | Read request signal for Ethernet control and status registers. |
i_reconfig_eth_writedata | 32 bits | Write request signal for Ethernet control and status registers. |
i_reconfig_eth_write | 1 bit | Write data for Ethernet control and status registers. |
o_reconfig_eth_readdata | 32 bits | Read data from reads to Ethernet control and status registers. |
o_reconfig_eth_readdata_valid | 1 bit | Read data from Ethernet control and status registers is valid. |
o_reconfig_eth_waitrequest | 1 bit | Avalon® memory-mapped interface stalling signal for operations on Ethernet control and status registers. |
This interface can access the entire address space of the Ethernet Hard IP. Refer to Appendix B: Configuration Registers for a description of the address space and links to all of the Ethernet Hard IP's status and control registers.