Visible to Intel only — GUID: piu1697543171811
Ixiasoft
Visible to Intel only — GUID: piu1697543171811
Ixiasoft
4.2. Implement Required Resets
The following table lists which blocks are reset by different reset signals:
Reset Signal | PHY | Datapath | Stats | Soft CSRs | |||||
---|---|---|---|---|---|---|---|---|---|
TX | RX | MAC TX | MAC RX | PCS TX | PCS RX | MAC TX | MAC RX | ||
Port Reset | |||||||||
i_rst_n | Y | Y | Y | Y | Y | Y | Y | Y | - |
i_tx_rst_n | Y | - | Y | - | Y | - | Y | - | - |
i_rx_rst_n | - | Y | - | Y | - | Y | - | Y | - |
i_reconfig_reset | - | - | - | - | - | - | - | - | Y |
Register Resets | |||||||||
eio_sys_rst | Y | Y | Y | Y | Y | Y | Y | Y | - |
soft_tx_rst | Y | - | Y | - | Y | - | Y | - | - |
soft_rx_rst | - | Y | - | Y | - | Y | - | Y | - |
rst_tx_stats | - | - | - | - | - | - | Y | - | - |
rst_rx_stats | - | - | - | - | - | - | - | Y | - |
The IP core has four asynchronous reset inputs, which are internally synchronized to their respective clock domains.
Signal | Description |
---|---|
Input signals | |
i_rst_n | Active-low reset asynchronous signal. Do not deassert until the o_rst_ack_n asserts. Refer to Table 21 for a list of blocks reset by this signal. This reset leads to assertion of the o_rst_ack_n output signal. |
i_tx_rst_n | Active-low reset asynchronous signal. Do not deassert until the o_tx_rst_ack_n asserts. |
i_rx_rst_n | Active-low reset asynchronous signal. Do not deassert until the o_rx_rst_ack_n asserts. |
i_reconfig_reset | Active-high reconfiguration reset signal. Resets the entire reconfiguration clock domain, including the soft registers (CSRs). You must assert this reset after power-on or during the IP configuration. The i_reconfig_clk must be stable before de-asserting this reset. |
Output signals | |
o_rst_ack_n | Active-low asynchronous acknowledgement signal for the i_rst_n reset. Do not deassert i_rst_n reset until the o_rst_ack_n asserts. |
o_tx_rst_ack_n | Active-low asynchronous acknowledgment signal for the i_tx_rst_n reset. Do not deassert i_tx_rst_n reset until the o_tx_rst_ack_n asserts. |
o_rx_rst_ack_n | Active-low asynchronous acknowledgement signal for the i_rx_rst_n reset. Do not deassert i_rx_rst_n reset until the o_rx_rst_ack_n asserts. |
Status signals | |
o_tx_lanes_stable | Active-high asynchronous status signal for the TX datapath.
|
o_rx_pcs_ready | Active-high asynchronous status signal for the RX datapath.
|