GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

4.6.1.1. Insert Alignment Marker

Figure 43. Insert Alignment Markers

When the PCS66 TX interface is used for FlexE mode, you can controll the timing of alignment marker insertion from the fabric.

For 10GE channels, the signal causes the cycle to be treated as invalid for PCS processing (no changes to scramble).

In FlexE mode, the timing of alignment marker insertion is very rigid. Alignment markers cannot be delayed without disrupting the Ethernet link. Use valid cycles to count the alignment markers. When i_tx_pcs66_valid is low, the alignment marker counters and input must freeze.

Assert i_tx_pcs66_am to have the TX PCS insert alignment markers. Without FEC, i_tx_pcs66_am is optional and tie the signal low.

In FEC modes, the TX datapath does not exit reset until at least two alignment marker periods pass. You must start driving i_tx_pcs66_am at the proper interval before o_tx_lanes_stable goes high. You can drive the signal as soon as o_tx_pll_locked is asserted ando_tx_pcs66_ready starts toggling.

The number of cycles for i_tx_mii_am to remain high depends on the rate of the interface, Specifically:
  • 25GE with RS-FEC: 4 cycles
The number of valid cycle for AM period depends on the rate of the interface and whether in simulation or hardware. In simulation, its common to use a reduced AM period for both sides of the link is commonly used to increase lock-time speed. Specifically:
  • 25GE with RS-FEC: 2552 (Non - PTP design)
  • 25GE with RS-FEC: 5112 (PTP Design)
In hardware: 25GE with RS-FEC: 81920