Visible to Intel only — GUID: jxq1702341222375
Ixiasoft
1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
Visible to Intel only — GUID: jxq1702341222375
Ixiasoft
A.4.2.2. PTP RX User Flow
The following flows depict pseudo-code meant for the conceptual, illustrative purposes. For definitive software routines, refer to the design example.
Note: The RX PTP Ready signal is deasserted when TX Reset is asserted. The RX PTP Ready signal asserts once TX Reset is released without the need to perform the initialization flow, provided the RX link is not lost or RX reset is not asserted during the TX Reset interval.
- After power on or RX reset or reestablish a lost RX link, wait until RX PCS is fully aligned.
Monitor the status via one of the following:
- Output port:
o_rx_pcs_fully_alligned = 1'b1
- Polling via Avalon® memory-mapped interface register until it is asserted:
For 10GE and 25G FEC variants:
csr_read(phy_rxpcs_status.rx_aligned) = 1’b1
- Output port:
- For FEC variants, configure RX FEC codeword position into the transceiver.
Attention: You must skip this step for non-FEC variants.
- Read RX FEC codeword position and FEC channel mapping for each PMA channel.
rx_fec_cw_pos = csr_read(rsfec_cw_pos_rx[fl][14:0])
- Calculate pulse adjustments.
rx_xcvr_if_pulse_adj = rx_fec_cw_pos
- Write the pulse adjustments into the IP:
csr_write(ux_q_dl_ctrl_a_l<apl>.cfg_rx_lat_bit_for_async[17:0], rx_xcvr_if_pulse_adj[pl*pl_fl_map])
Note: Each bank has one actual physical channel. You must program the registers of all active bank channels. - Notify soft PTP that pulse adjustments have been configured.
csr_write(ptp_rx_user_cfg_status.rx_fec_cw_pos_cfg_done, 1'b1)
- Read RX FEC codeword position and FEC channel mapping for each PMA channel.
- Wait until RX raw offset data are ready.
You can monitor the status via one of the following:
- Output port:
o_rx_ptp_offset_data_valid = 1'b1
- Polling via CSR:
csr_read(ptp_status.rx_ptp_offset_data_valid) = 1’b1
- Output port:
- Read RX raw offset data from IP:
- All variants:
rx_const_delay = csr_read(ptp_rx_lane_calc_data_constdelay[30:0]) rx_const_delay_sign = csr_read(ptp_rx_lane_calc_data_constdelay[31]) rx_apulse_offset = csr_read(ptp_rx_lane_calc_data_offset[30:0]) rx_apulse_offset_sign = csr_read(ptp_rx_lane_calc_data_offset[31]) rx_apulse_wdelay] = csr_read(ptp_rx_lane_calc_data_wiredelay[19:0])
- 10GE/25GE no FEC variants:
rx_bitslip_cnt = csr_read(bitslip_cnt.bitslip_cnt[6:0]) rx_dlpulse_alignment = csr_read(bitslip_cnt.dlpulse_alignment)
- All variants:
- Determine synchronous pulse AM offsets with reference to asynchronous pulse.
- FEC variants:
rx_spulse_offset = rx_xcvr_if_pulse_adj[4:0] * UI rx_spulse_offset_sign = 1'b0;
- FEC variants:
- Calculate RX offsets:
- Calculate RX TAM adjust:
FEC variants:
rx_tam_adjust = (rx_const_delay_sign ? –rx_const_delay : rx_const_delay) + (rx_apulse_offset_sign ? –rx_apulse_offset : rx_apulse_offset – (rx_apulse_wdelay) + (rx_spulse_offset_sign ? -rx_spulse_offset[rx_ref_fl] : rx_spulse_offset[rx_ref_fl])
For all other cases:rx_tam_adjust = rx_tam_adjust_sim
Convert TAM adjust to a 32-bit 2's complement number:
rx_tam_adjust_2c = rx_tam_adjust where rx_tam_adjust is a 32-bit 2's complement number
- Calculate RX extra latency:
Convert unit of RX PMA delay from UI to nanoseconds:
rx_pma_delay_ns = rx_pma_delay_ui * UI5
RX extra latency is a negative adjustment. To indicate the negative adjustment, set the most-significant register bit to 1. Total up all extra latency together:rx_extra_latency[30:0] = rx_pma_delay_ns + rx_external_phy_delay
rx_extra_latency[31] = 1'b1
- Calculate RX TAM adjust:
- Write the calculated RX offsets to IP:
- Write RX extra latency:
csr_write(rx_ptp_extra_latency, rx_extra_latency)
- Write RX TAM adjust:
csr_write(ptp_rx_tam_adjust, rx_tam_adjust_2c)
- Write RX extra latency:
- Notify soft PTP that uses flow configuration is completed.
csr_write(ptp_rx_user_cfg_status.rx_user_cfg_done, 1'b1)
- Continue UI value measurement. Follow steps 1 through 7 mentioned in the RX UI Adjustment section.
For simulation or hardware run with 0 PPM setup, you can skip the measurement and program 0 PPM UI value defined in UI Adjustment.
- Wait until RX PTP is ready.
You can monitor the status via one of the following:
- Output port:
o_rx_ptp_ready = 1'b1
- Polling via CSR:
csr_read(ptp_status.rx_ptp_ready) = 1’b1
- Output port:
- RX PTP is up and running.
Adjust RX UI value.
Perform the RX UI adjustment occasionally to prevent time counter drift from golden time-of-day in the system. Follow steps 1 through 8 described in RX UI Adjustment.
Note: UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends skipping this step and program a 0 PPM value. For more details, refer to UI Value and PMA Delay.
5 The UI format differs from the format of other variables. UI uses the {4-bit ns, 28-bit fractional ns} format. Other variables defined in this flow use the {N-bit ns, 16-bit fractional ns} format, where N is the largest number to store the calculation's max value. If you use UI format in your calculation, you must convert your result to a 16-bit fractional ns format.