GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

A.4.2.1. PTP TX User Flow

The following flows depict pseudo-code meant for the conceptual, illustrative purposes. For definitive software routines, refer to the design example.

Important: If IP undergoes TX reset at any point in this flow, you must restart the entire PTP TX client flow.
  1. After power up or a TX reset, wait until TX raw offset data are ready.
    Monitor the status via one of the following:
    • Output port:
      o_tx_ptp_offset_data_valid = 1'b1
    • Polling via Avalon® memory-mapped interface register until it is asserted:
      csr_read(ptp_status.tx_ptp_offset_data_valid) = 1’b1
  2. Read TX raw offset data from IP:
    tx_const_delay      = csr_read(ptp_tx_lane_calc_data_constdelay[30:0])
    tx_const_delay_sign = csr_read(ptp_tx_lane_calc_constdelay[31])
    tx_apulse_offset = csr_read(ptp_tx_lane_calc_data_offset[30:0])
     tx_apulse_offset_sign = csr_read(ptp_tx_lane_calc_data_offset[31])
     tx_apulse_wdelay = csr_read(ptp_tx_lane_calc_data_wiredelay[19:0]) }
  3. Calculate TX offsets:
    1. Calculate TX TAM adjust:
      tx_tam_adjust = 
        (tx_const_delay_sign ? –tx_const_delay : tx_const_delay)
      + (tx_apulse_offset_sign? 
            –tx_apulse_offset : tx_apulse_offset)
      – (tx_apulse_wdelay)
      
      Note: Convert TAM adjust to a 32-bit 2's complement number:
      tx_tam_adjust_2c = tx_tam_adjust
      
    2. Calculate TX extra latency:
      Convert unit of TX PMA delay from UI to nanoseconds. For UI value, refer to tables specified in UI Value and PMA Delay.
      tx_pma_delay_ns = tx_pma_delay_ui * UI4
      TX extra latency is a positive adjustment. To indicate the positive adjustment, set the most-significant register bit to 0. Total up all extra latency together:
      tx_extra_latency[31] = 1'b0
      tx_extra_latency[30:0] = tx_pma_delay_ns + tx_external_phy_delay
  4. Write the calculated TX offsets to IP:
    1. Write TX extra latency:
      csr_write(tx_ptp_extra_latency, tx_extra_latency)
    2. Write TX TAM adjust:
      csr_write(ptp_tx_tam_adjust, tx_tam_adjust_2c)
  5. UI value measurement. Follow the steps mentioned in the Adjust TX UI section.

    For simulation or hardware run with 0 PPM setup, you can skip the measurement and program 0 PPM UI value defined in UI Adjustment.

  6. Notify soft PTP that the user flow configuration is complete.
    csr_write(ptp_tx_user_cfg_status.tx_user_cfg_done, 1'b1)
  7. Wait until TX PTP is ready.
    You can monitor the status via one of the following:
    • Output port:
      o_tx_ptp_ready = 1'b1
    • Polling via CSR:
      csr_read(ptp_status.tx_ptp_ready) = 1’b1
  8. TX PTP is up and running.

    Adjust TX UI value.

    Perform the TX UI adjustment occasionally to prevent time counter drift from golden time-of-day in the system. Follow the steps described in Adjust TX UI.

    Note: UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends skipping this step and program a 0 PPM value.
4 The UI format differs from the format of other variables. UI uses the {4-bit ns, 28-bit fractional ns} format. Other variables defined in this flow use the {N-bit ns, 16-bit fractional ns} format, where N is the largest number to store the calculation's maximum value. If you use UI format in your calculation, you must convert your result to a 16-bit fractional ns format.