Visible to Intel only — GUID: rej1717718776216
Ixiasoft
Visible to Intel only — GUID: rej1717718776216
Ixiasoft
11.3. Use Signal Tap Analyzer for Troubleshooting
- Navigate to Tools > Signal Tap Logic Analyzer to launch the Signal Tap Analyzer.
- In the User Processing option, select Run Analysis.
The following table lists the debug signals and their descriptions:
Signals | Description | Action |
---|---|---|
Reset Signals | ||
o_rst_ack_n | Active-low asynchronous acknowledgment signal for the i_rst_n reset. Do not deassert i_rst_n reset until the o_rst_ack_n asserts. |
— |
o_tx_rst_ack_n | Active-low asynchronous acknowledgment signal for the i_tx_rst_n reset. Do not deassert i_tx_rst_n reset until the o_tx_rst_ack_n asserts. |
— |
o_rx_rst_ack_n | Active-low asynchronous acknowledgment signal for the i_rx_rst_n reset. Do not deassert i_rx_rst_n reset until the o_rx_rst_ack_n asserts. |
— |
o_src_rs_req | Request from GTS Ethernet Hard IP to GTS Reset Sequencer Intel® FPGA IP for reset exit | |
o_rx_block_lock | Asserted when 66b block alignment is finished on all PCS virtual lanes. | |
o_local_fault_status | The RX PCS channel has detected a problem that prevents it from being able to receive data. | |
o_remote_fault_status | The remote link partner has sent remote fault ordered sets indicating that it is unable to receive data. | |
rx_lane_current_status | Current status of RX reset sequence | If the rx_lane_current_status ≠ 0x01 state (operational state), refer to the Debug in Reset Sequence. |
tx_lane_current_status | Current status of TX reset sequence | |
o_tx_lanes_stable | Active-high asynchronous status signal for the TX datapath. Asserts when the TX datapath is ready to send data. Deasserts when i_tx_rst_n or i_rst_n signal asserts or during the auto-negotiation and link training operation. |
|
o_rx_pcs_fully_aligned | Asserted when RX PCS is ready to receive data in PCS66 and PCS Only modes. |
— |
o_rx_pcs_ready | Active-high asynchronous status signal for the RX datapath. Asserts when the RX datapath is ready to send data. Deasserts when i_rx_rst_n or i_rst_n signal asserts or during the auto-negotiation and link training operation. |
Check the CDR lock,0_clk_rec_div64 and o_clk_rec_div and XVIF RX FIFO status (Refer to the GTS Ethernet Hard IP Register Map to access XVIF FIFO Status) |
Clock Signals | ||
o_cdr_lock | CDR locked | Indicates that the recovered clocks are locked to data. Do not use o_clk_rec_div64 or o_clk_rec_div until o_cdr_lock is high. |
o_sys_pll_locked | Verify if the System PLL is locked. Check if the system PLL output frequency is correct. |
Refer to Implement Required Clocking |
o_tx_pll_locked | Verify that the TX PLL lock is asserted. |