GTS Ethernet Intel® FPGA Hard IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817676
Date 4/07/2025
Public

Visible to Intel only — GUID: ncj1697542992527

Ixiasoft

Document Table of Contents

4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances

Perform the following clock connections for multiple IP Instance of GTS Ethernet Intel® FPGA Hard IP :

Figure 17. Clock Connections for Multiple IP Instances
  • Configure all instantiated GTS Ethernet Intel® FPGA Hard IP at the same rate.
  • Connect o_syspll_c0 output clock of GTS System PLL Clocks Intel FPGA IP to i_clk_sys of GTS Ethernet Intel® FPGA Hard IPs.
  • Connect PMA reference clock to i_clk_ref_p of all GTS Ethernet Intel® FPGA Hard IPs.
  • Connect the output clock o_clk_pll to i_clk_rx and i_clk_tx input clocks of all GTS Ethernet Intel® FPGA Hard IPs.
  • Connect i_refclk of GTS System PLL Clocks Intel® FPGA IP to any of the local or regional reference clock source.
  • The i_clk_ref_p of GTS Ethernet Intel® FPGA Hard IP and i_refclk of GTS System PLL Clocks Intel® FPGA IP can share the same clock source.
  • Provide the required clock source to i_reconfig_clk. The i_reconfig_clk signal is shared between all the GTS Ethernet Hard IP instances.