Visible to Intel only — GUID: cvp1715721020193
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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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6.3.1. Simulation Testbench Flow
The testbench executes the following activities for various modes, including PCS, OTN, and FlexE:
- Assert global reset (i_rst_n) to reset the GTS Ethernet Intel® FPGA Hard IP .
- Wait until reset acknowledgment. The o_rst_ack_n signal goes low.
- Deassert the global reset.
- Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
- Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
- Instruct packet client to transmit data. Write cfg_start_pkt_gen[0]=1'b1 to start the packet generator.
Note: The packet client sends out idle data in MII/PCS66 format when no packet is being transmitted.
- Read RX packet data information from 0x38 - 0x4C registers in sequential order:
- 0x00: Set snapshot enable bit to read the RX packet statistics (set bit 6 of hw_pc_ctrl register 0x00 to 1'b1
- 0x38/0x3C: RX start of packet counter (LSB/MSB)
- 0x40/0x44: RX end of packet counter (LSB/MSB)
- 0x48/0x4C: RX error counter (LSB/MSB)
- 0x00: Disable snapshot bit (set bit 6 of hw_pc_ctrl register 0x00 to 1'b0
- Read TX packet data information from 0x00 - 0x34 registers in sequential order:
- 0x00: Set snapshot enable bit to read the TX packet statistics (set bit 6 of hw_pc_ctrl register = 1'b1 to 0x00 to 1'b1
- 0x20/0x24: TX start of packet counter (LSB/MSB)
- 0x28/0x2C: TX end of packet counter (LSB/MSB)
- 0x00: Disable snapshot bit (set bit 6 of hw_pc_ctrl register 0x00 to 1'b0
- Compare the counters to ensure 16 packets were sent and received.
- Instruct packet client to stop data transmission. Write cfg_start_pkt_gen[0]=1'b0 to stop the packet generator.
- Write 0x1 to cfg_clear_counters to clear the packet generator counter.
- Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers:
- 0x104: Scratch register
- 0x108: Ethernet IP soft reset register
- 0x004: Ethernet IP debug configuration control register
- 0x008: Ethernet IP enable/clock gating configuration register
- Perform Avalon® memory-mapped interface 2 test. Write and read transceiver registers.