GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

6.3.1. Simulation Testbench Flow

The testbench executes the following activities for various modes, including PCS, OTN, and FlexE:
  1. Assert global reset (i_rst_n) to reset the GTS Ethernet Intel® FPGA Hard IP .
  2. Wait until reset acknowledgment. The o_rst_ack_n signal goes low.
  3. Deassert the global reset.
  4. Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
  5. Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
  6. Instruct packet client to transmit data. Write cfg_start_pkt_gen[0]=1'b1 to start the packet generator.
    Note: The packet client sends out idle data in MII/PCS66 format when no packet is being transmitted.
  7. Read RX packet data information from 0x38 - 0x4C registers in sequential order:
    1. 0x00: Set snapshot enable bit to read the RX packet statistics (set bit 6 of hw_pc_ctrl register 0x00 to 1'b1
    2. 0x38/0x3C: RX start of packet counter (LSB/MSB)
    3. 0x40/0x44: RX end of packet counter (LSB/MSB)
    4. 0x48/0x4C: RX error counter (LSB/MSB)
    5. 0x00: Disable snapshot bit (set bit 6 of hw_pc_ctrl register 0x00 to 1'b0
  8. Read TX packet data information from 0x00 - 0x34 registers in sequential order:
    1. 0x00: Set snapshot enable bit to read the TX packet statistics (set bit 6 of hw_pc_ctrl register = 1'b1 to 0x00 to 1'b1
    2. 0x20/0x24: TX start of packet counter (LSB/MSB)
    3. 0x28/0x2C: TX end of packet counter (LSB/MSB)
    4. 0x00: Disable snapshot bit (set bit 6 of hw_pc_ctrl register 0x00 to 1'b0
  9. Compare the counters to ensure 16 packets were sent and received.
  10. Instruct packet client to stop data transmission. Write cfg_start_pkt_gen[0]=1'b0 to stop the packet generator.
  11. Write 0x1 to cfg_clear_counters to clear the packet generator counter.
  12. Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers:
    • 0x104: Scratch register
    • 0x108: Ethernet IP soft reset register
    • 0x004: Ethernet IP debug configuration control register
    • 0x008: Ethernet IP enable/clock gating configuration register
  13. Perform Avalon® memory-mapped interface 2 test. Write and read transceiver registers.