GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public
Document Table of Contents

3.5.1. Directory Structure

The GTS Ethernet Intel® FPGA Hard IP core design example contains the following generated files.
Figure 9. Directory Structure for GTS Ethernet Intel® FPGA Hard IP Design ExampleThe <ethernet_mode> refers to the selected Ethernet mode in the IP tab of the IP parameter editor.
Table 15.  Directory and File Description
Directory/File Description
<design_example_dir>/hardware_test_design/intel_eth_gts_hw.qpf Quartus® Prime project file.
<design_example_dir>/hardware_test_design/intel_eth_gts_hw.qsf Quartus® Prime setting file.
<design_example_dir>/hardware_test_design/intel_eth_gts_hw.v Design example top-level HDL.
<design_example_dir>/hardware_test_design/intel_eth_gts_hw.sdc Synopsys Design Constraints (SDC) file.
<design_example_dir>/hardware_test_design/common Hardware design example support files.
<design_example_dir>/example_testbench/basic_avl_tb_top.sv Testbench file
<design_example_dir>/example_testbench/run_vcsmx.sh Simulation script file for VCS* MX Simulator
<design_example_dir>/example_testbench/run_vsim.do Simulation script file for Questasim Simulator
<design_example_dir>/example_testbench/run_xcelium.sh Simulation script file for Xcelium* Simulator
<design_example_dir>/hardware_test_design/hwtest/main_<eth_rate>.tcl Hardware design example TCL file
The Quartus® Prime software generates the design example files in the following folders:
  • <design_example_dir>/ex_<datarate>: IP core files
  • <design_example_dir>/example_testbench: simulation files for testbench
  • <design_example_dir>/hardware_test_design: hardware test design files