GTS Ethernet Intel® FPGA Hard IP User Guide

ID 817676
Date 8/05/2024
Public

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11.2. Troubleshoot the Reset Sequence

The following section outlines the reset process steps, which are illustrated in a flow chart that explains the sequence of reset actions. Each state in the flow chart, along with its corresponding tx_lane_current and rx_lane_current_state, provides you with precise insights into the reset process, facilitating easier debugging if needed.