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1. Overview
2. Install and License the GTS Ethernet Intel® FPGA Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Intel® FPGA Hard IP into Your Application
5. Simulate, Compile, and Validate (MAC+PCS) - Single Instance
6. Simulate, Compile, and Validate (MII PCS Only /PCS66 OTN/PCS66 FlexE) - Single Instance
7. Simulate, Compile, and Validate SyncE - Single Instance
8. Simulate and Compile PTP1588 - Single Instance
9. Simulate, Compile, and Validate - Multiple Instance
10. Simulate, Compile, and Validate - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
A. Appendix A: Functional Description
B. Appendix B: Configuration Registers
C. Appendix C: Document Revision History for the GTS Ethernet Intel® FPGA Hard IP User Guide
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.1.1. Implement MAC Synchronous Clock Connections to Single Instance
4.1.2. Implement MAC Synchronous Clock Connections to Multiple Instances
4.1.3. Implement Clock Connections to MAC Asynchronous Operation
4.1.4. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E)
4.1.5. Implement Clock Connections in PTP-Based Design
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
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8.3.1. Simulation Testbench Flow
The testbench executes the following activity for MAC with PTP enabled mode:
- Assert global reset (i_rst_n) to reset the GTS Ethernet Intel® FPGA Hard IP.
- Wait until reset acknowledgment. The o_rst_ack_n signal goes low.
- Deassert the global reset.
- Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
- Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
- Perform the PTP user flow until tx_ptp_ready and rx_ptp_ready signals are set to 1.
- Write to PTP Asymmetry Delay and peer-to-peer MeanPathDelay Avalon® memory-mapped interface registers.
- Reset the PTP monitor.
- Instruct packet client to transmit data. Write 0x1 to bit 0 of hardware packet client control hw_pc_ctrl register 0x00 to start packet generator.
- Read RX packet data information from 0x38 - 0x4C registers in sequential order.
- 0x00: Set hw_pc_ctrl[6] = 1'b1 to enable snapshot bit to read the RX packet statistics.
- 0x38/0x3C: RX start of packet counter (LSB/MSB)
- 0x40/0x44: RX end of packet counter (LSB/MSB)
- 0x48/0x4C: RX error counter (LSB/MSB)
- 0x00: Set hw_pc_ctrl[6] = 1'b0 to disable snapshot bit.
- Read TX packet data information from 0x00 - 0x34 registers in sequential order.
- 0x00: Set hw_pc_ctrl[6] = 1'b1 to enable snapshot bit to read the TX packet statistics.
- 0x20/0x24: TX start of packet counter (LSB/MSB)
- 0x28/0x2C: TX end of packet counter (LSB/MSB)
- 0x30/0x34: TX error counter (LSB/MSB)
- 0x00: Set hw_pc_ctrl[6] = 1'b0 to disable snapshot bit.
- Compare read counters to ensure 16 packets were sent and received.
- Instruct packet client to stop data transmission and clear the counters by writing hw_pc_ctrl[2:0]=3'b100 to stop the packet generator.
- Start the PTP checker.
- Wait until the packet transmission is complete. Poll the TX_PKT_VALID bit to monitor the transmission status.
- Read TX packet data information from 0x102 - 0x104 registers in sequential order, starting from the 0x102 register. The PTP monitor logic refreshes the 0x102 - 0x104 registers content to next data when read from 0x104 register.
- Repeat the previous step until the TX_PKT_EOP bit is set to 1 indicating the read operation reached the end of the packet.
- Read TX PTP command information from 0x105 - 0x10A registers in sequential order, starting from the 0x105 register. The PTP monitor logic refreshes the 0x105 - 0x10A registers content to next data when read from 0x10A register.
- If TX PTP command indicates a PTP packet:
- Wait until the TX egress timestamp is available. Use the TX_PTP_ETS_VALID signal to monitor the status.
- Read the TX egress timestamp from the 0x10C - 0x10F registers in sequential order, starting with the 0x10C register.
- Wait until the packets are looped backe in the RX data path. Poll the RX_PKT_VALID bit to monitor the transmission status.
- Read RX packet data information from 0x110 - 0x112 registers in sequential order, starting with the 0x110 register. The PTP monitor logic refreshes the 0x110 - 0x112 registers content to next data when read from 0x112 register.
- Repeat the previous step until the RX_PKT_EOP bit is set to 1 indicating the read operation reached the end of the packet.
- Read RX ingress timestamp.
- Read the RX ingress timestamp from the 0x114 - 0x116 registers in sequential order, starting with the 0x14 register. The PTP monitor logic refreshes the 0x114 - 0x116 registers content to next data when read from 0x116 register.
- Display the TX packet content, RX packet content, TX PTP commands, TX egress timestamp, and RX ingress timestamp information.
- Display the comparison information. Note that in 1-step commands, the TX/RX packets and PTP commands field content is the same.
- Repeat steps b through step k until the system processes all packets.
Note: The design example simulation performs step 14 for only first six packets to reduce long simulation time.
- Perform Avalon® memory-mapped interface test on PTP-related registers.
- Selective PTP Asymmetry Delay and P2P MeanPathDelay registers
- Selective Master TOD Avalon® memory-mapped interface registers
- Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers.
- 0x104: Scratch register
- 0x108: Ethernet IP soft reset register
- 0x214: TX MAC source address register [31:0]
- 0x218: TX MAC source address register [47:32]
- 0x21C: RX MAC frame size register
- Perform Avalon® memory-mapped interface 2 test. Write and read transceiver registers.