GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

A.1.1. Debugging Link Training Issues

The Physical Layer automatically performs link training and initialization without software intervention. This is a well-defined process to configure and initialize the device's Physical Layer and link so that PCIe* packets can be transmitted.

Some examples of link training issues include:
  • Link fails to negotiate to expected link speed.
  • Link fails to negotiate to the expected link width.
  • LTSSM fails to reach/stay stable at L0.
Figure 72. Link Training Debugging Flow
Note: (*) Redo the equalization using the Link Equalization Request 8.0 GT/s bit of the Link Status 2 register for 8.0 GT/s or Link Equalization Request 16.0 GT/s bit of the 16.0 GT/s Status Register.

Use the following debug tools for debugging link training issues observed on the PCI Express* link when using the GTS AXI Streaming IP.