GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

4.16. Single Root I/O Virtualization (SR-IOV)

The GTS AXI Steamig IP suppots SR-IOV. The edpoit pot cotolles i the IP suppot up to 4 physical fuctios (PF) ad 256 vitual fuctios (VF) pe SR-IOV edpoit. The VF cofiguatio space egistes ae hadeed i the PCIe* Had IP; hece they do ot equie FPGA fabic esouces. The specific VF-based wok queues ad iteupt tables must be implemeted i the FPGA fabic by the use applicatio.

Table 22.  Sigle Root I/O Suppoted Featues List
Featue Suppot
SR-IOV

Suppoted i Edpoit mode up to 256 VFs.
MSI

Suppoted i PFs oly. Not suppoted i VFs.

No Pe Vecto Maskig (PVM). If you eed PVM, you must use MSI-X.

Note: Note: Whe SR-IOV is eabled, eithe MSI o MSI-X must be eabled.
MSI-X

Suppoted by all PFs.

Fo SR-IOV, PFs ad VFs ae always MSI-X capable.

Note: VFs shae a commo Table Size. VF Table BIR/Offset ad PBA BIR/Offset ae fixed at compile time.
Note: Whe SR-IOV is eabled, eithe MSI o MSI-X must be eabled.
Fuctio Level Reset (FLR) Suppoted by all PFs/VFs.
Requied fo all SR-IOV fuctios.
Exteded Tags

Suppoted by all PFs/VFs. The Exteded Tags featue allows the TLP Tag field to be 8-bit, thus allowig the suppot of 256 tags.

The applicatio is esticted to a max of 256 outstadig tags, at ay give time, fo all fuctios combied.

The applicatio logic is esposible fo implemetig the tag geeatio/tackig fuctios.
10-bit Tags

Suppots 10-bit tag complete capability o x8 capable cotolle.
AER

PFs ae always AER capable. No AER implemeted fo VFs.
Active-State Powe Maagemet (ASPM) Optioality Compliace

Suppoted by all PFs/VFs.

Oly used to idicate ASPM is suppoted.
Atomic Ops

Requeste capability is suppoted by all PFs/VFs.

Complete capability is suppoted.

Compae ad Swap (CAS) AtomicOps ae also suppoted. They ca hadle up to 128-bit opeads.
Iteal Eo Repotig

Suppoted by all PFs (because all PFs ae AER capable).

No suppot fo VFs (because VFs do ot suppot AER).
TLP Pocessig Hits

2-bit Pocessig Hit ad 8-bit Steeig Tag ae suppoted by all PFs/VFs.

TPH Pefixes ae ot suppoted.

You ca optioally choose to eable the TPH Requesto capability. Howeve, the IP is always TPH Complete capable.
ID-Based odeig

Suppoted by all PFs/VFs.

Howeve, the IP coe does NOT pefom the eodeig. The Applicatio Laye must do the eodeig.

The IP coe oly povides the IDO Request & Completio Eable bits i the Device Cotol 2 egiste. This gives the applicatio pemissio to set the Att bits i Requests ad Completios that it tasmits.

Note: Reodeig capability o the RX side may be limited by you bypass queue. O the TX side, the IP coe does ot set the IDO bits o iteally geeated TLPs.
Relaxed Odeig

Implemeted o the RX side. This featue is always active.

O the TX side, eodeig is doe by the applicatio.
Alteative Routig ID Itepetatio (ARI)

EP (PFs/VFs) is always ARI capable. This is a device-level optio (all laes o oe suppot ARI).

I additio, RP is always ARI capable (ARI Fowadig Suppoted bit is always 1).
Addess Taslatio Sevice (ATS) Suppoted by all EP PFs/VFs.
Page Request Sevice Iteface (PRI) Suppoted by all EP PFs/VFs.
Use Extesios (Custome VSEC) Suppoted by all PFs/VFs.
PCIe* 3.0 Receive Impedace (3.0 ECN) Suppoted
Device Seial Numbe Suppoted
Completio Timeout Rages (Device Capabilities 2) All ages ae suppoted.
Data Lik Laye Active Repotig Capability (Lik Capabilities) This capability is always suppoted i RP mode, but ot i EP mode.
Supise Dow Eo Repotig Capability (Lik Capabilities) Suppoted
PM-PCI Powe Maagemet Oly D0/D3 states ae suppoted.
ASPM (L0s/L1) Suppoted
Pocess Addess Space ID (PASID) Suppoted
TLP pefix Suppoted, maily fo PASID
Latecy Toleace Repotig (LTR) Suppoted (oly fo PASID)
Access Cotol Sevices Suppoted
Advaced Eo Repotig (AER) AER suppoted fo PFs.

Sectio Cotet
SR-IOV Implemetatio

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