GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

Documet Vesio Quatus® Pime Vesio IP Vesio Chages
2024.11.04 24.3 6.0.0 Made the followig chages:
  • Updated the Suppoted Featues topic with ew featue suppot.
  • Updated the Featue Suppot Status table with ew featue suppot.
  • Updated the Agilex™ 5 Recommeded FPGA Fabic Speed Gades fo All AXI-Steam Width ad Fequecies table with the ecommeded FPGA fabic speed gades.
  • Updated the Completio Buffe Size table i the TX No-Posted Meteig Requiemet o Applicatio sectio with Pot 1 ifomatio fo D-Seies devices.
  • Updated the Cedit Advetised by GTS AXI Steamig IP table i the TX No-Posted Meteig Requiemet o Applicatio sectio with x8 cotolle ifomatio.
  • Added ew sectio Powe Maagemet i the IP Achitectue ad Fuctioal Desciptio chapte.
  • Added ew sectio Cofig Rety Status Eable i the IP Achitectue ad Fuctioal Desciptio chapte.
  • Added ew sectio Hot-Plug i the IP Achitectue ad Fuctioal Desciptio chapte.
  • Added ew sectio Cofiguatio Space Extesio i the IP Achitectue ad Fuctioal Desciptio chapte.
  • Added ew sectio Page Request Sevice (EP oly) i the IP Achitectue ad Fuctioal Desciptio chapte.
  • Combied the E-Seies ad D-Seies IP Paametes chaptes.
  • Updated the IP Paametes chapte extesively with chapte eogaizatio ad additio of ew featue paamete tabs.
  • Updated the GTS AXI Steamig IP—Top-Level Sigals figue i the Oveview sectio.
  • Updated sigal ames i the Iteface Clock Sigals sectio.
  • Removed the i_gpio_pest0/1_ sigals fom the Iteface Reset Sigals sectio.
  • Added ew sectio Cofiguatio Extesio Bus Iteface i the Itefaces ad Sigals chapte.
  • Updated the Completio Timeout Iteface sectio i the Itefaces ad Sigals chapte.
  • Coected typogaphical eo i the Fuctio Level Reset Received Iteface sectio i the Itefaces ad Sigals chapte.
  • Added ew sectio Eo Iteface i the Itefaces ad Sigals chapte.
  • Added ew sectio VIRTIO PCI Cofiguatio Access Iteface i the Itefaces ad Sigals chapte.
  • Updated the Cotol Registe Addess Map table i the Cotol Registes sectio with ifomatio about hot plug ad powe maagemet cotol egistes.
  • Added Appedix C. Implemetatio of Addess Taslatio Sevices (ATS) i Edpoit Mode with ifomatio about the Addess Taslatio Sevices.
2024.08.07 24.2 5.0.0 Made the followig chages:
  • Updated the Featue Suppot Status table with ifomatio about PCIe* 4.0 x8, PCIe* 3.0 x8, lae evesal, FASTSIM, ad PIPE mode suppot.
  • Updated the Resouce Utilizatio fo GTS AXI Steamig IP fo Agilex™ 5 Devices table.
  • Updated the Agilex™ 5 Recommeded FPGA Fabic Speed Gades fo All AXI-Steam Width ad Fequecies table with the ecommeded FPGA fabic speed gades.
  • Added ote i Recommeded FPGA Fabic Speed Gades about speed gades suppoted fo PCIe* 4.0.
  • Updated the GTS AXI Steamig IP Suppot Matix fo Agilex™ 5 Device table with PCIe* 4.0 x8 ad PCIe* 3.0 x8 suppot levels.
  • Added ifomatio about PCIe* 4.0 x8 ad PCIe* 3.0 x8 suppot i seveal tables ad figues.
  • Updated the IP Achitectue ad Fuctioal Desciptio sectio with ifomatio about Agilex™ 5 D-Seies FPGA suppot fo PCIe* x8 o x4 ad efeece clock equiemets.
  • Added ifomatio about Agilex™ 5 D-Seies FPGA suppot i seveal sectios.
  • Updated the Coectig Clock ad Reset Sigals of GTS AXI Steamig IP figue with ew sigal ad pot ames.
  • Updated the Clockig sectio with ifomatio about suppoted pld_clk fequecies fo PCIe* Ge4 x8 ad PCIe* 3.0 x8 suppot.
  • Updated the Resets sectio extesively ad added a ew table Pi Locatio Assigmet fo p0_pi_pest__i ad p0_pi_pest__1_i Pots.
  • Updated the Resets sectio extesively ad added a ew table Pi Locatio Assigmet fo p0_pi_pest__i ad p0_pi_pest__1_i Pots.
  • Updated the PCIe* Had IP sectio with a ew figue Agilex™ 5 PCIe* 4.0 x8 Had IP Block Diagam fo D-Seies FPGAs ad ifomatio about the Agilex™ 5 D-Seies FPGAs.
  • Updated the timig diagam figues i the Iteupts sectio with coected sigal ames.
  • Updated IP Paametes chapte ame to IP Paametes fo E-Seies FPGA.
  • Updated the GTS AXI Steamig IP Paametes: PCIe* Itefaces 0 Settigs Tab table with ew Eable CVP (Itel VSEC) ad Eable Cofiguatio Itecept Iteface Moito paametes.
  • Updated the GTS AXI Steamig IP Paametes: PCIe* 0 Base Addess Registes Tab table with BAR<> size paamete value.
  • Updated the GTS AXI Steamig IP Paametes: PCIe* 0 PCI Expess* / PCI Capabilities Tab0 table with PF<> Eable MSI paamete value.
  • Added ew chapte IP Paametes fo D-Seies FPGAs.
  • Updated all the sectios i the Itefaces ad Sigals chapte ad eplaced p0 i the tables ad figues with p<> as suppot is added fo two pots: pot 0 ad pot 1.
  • Updated the Iteface Clock Sigals table with ew clock sigals ad suppoted fequecies fo x8 modes.
  • Updated the Iteface Reset Sigals table with ew eset sigals ad desciptios.
  • Updated the eset sequece desciptios i the Iteface Reset Sigals sectio.
  • Updated the desciptios fo p<>_ss_app_vf_e_oveflow ad p<>_ss_app_vfofatalmsg_eady sigals i the VF Eo Flag Iteface table.
  • Updated the desciptio fo p<>_ss_app_supise_dow_e sigal i the Miscellaeous Sigals table.
  • Removed the details of the egistes fom seveal sectios i the Registes chapte ad added lik to the Excel-based egiste map.
  • Updated the Registes chapte with a ew sectio Itel-Defied VSEC Capability Registe.
  • Updated the Lauchig the Debug Toolkit sectio with ew image fo iitializatio.
  • Updated the Eye Viewe topic i Usig the Agilex™ 5 Debug Toolkit with details about usig the Eye Viewe tool.
  • Added Appedix B. PIPE Mode Simulatio with ifomatio about PIPE mode simulatio details.
2024.05.15 24.1 4.0.0 Coected the ecommeded FPGA fabic speed gades fo the PCIe* 3.0 x2 lik cofiguatio i Table: Agilex™ 5 Recommeded FPGA Fabic Speed Gades fo All AXI-Steam Width ad Fequecies.
2024.05.10 24.1 4.0.0 Iitial elease.
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