Visible to Intel only — GUID: wwo1701310334942
Ixiasoft
Visible to Intel only — GUID: wwo1701310334942
Ixiasoft
A.1.1.2. Signal Tap Logic Analyzer
Using the Signal Tap logic analyzer, you can monitor the following top-level signals from the GTS AXI Streaming IP to confirm the failure symptom for any port type (Root Port, Endpoint, or TLP Bypass) and configuration ( PCIe* 4.0/ PCIe* 3.0).
Signals | Description | Expected Value for Successful Linkup |
---|---|---|
p0_pin_perst_n |
Active-low asynchronous output signal from the PCIe* Hard IP. It is derived from the pin_perst_n input signal. |
1'b1 |
p0_reset_status_n |
Active-low output signal from the PCIe* Hard IP, synchronous to coreclkout_hip_toapp. Held low until pin_perst_n is deasserted and the PCIe* Hard IP comes out of reset. |
1'b1 |
ninit_done |
Active-low output signal from the Reset Release Intel® FPGA IP. High indicates that the FPGA device is not yet fully configured, and low indicates the device has been configured and is in normal operating mode. For more details about the Reset Release Intel® FPGA IP, refer to Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs . |
1'b0 |
p0_ss_app_linkup |
Active-high output signal from the PCIe* Hard IP, synchronous to coreclkout_hip_toapp. Indicate that the Physical Layer link is up. |
1'b1 |
p0_ss_app_dlup |
Active-high output signal from the PCIe* Hard IP, synchronous to coreclkout_hip_toapp. Indicate that the Data Link Layer is active. |
1'b1 |
p0_ss_app_ltssmstate[5:0] |
Indicates the LTSSM state, synchronous to coreclkout_hip_toapp. |
6'h11 (S_L0) |