GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

6.6. Control Shadow Interface

The cotol shadow iteface bigs out the settigs of the vaious cofiguatio egiste fields of the fuctio. These fields ae madatoy to desig the cotol path of the applicatio laye logic.

The applicatio logic decodes ifomatio povided o this iteface to ceate a shadow copy. The iteface povides update to pimay cotol sigals oly. The applicatio logic must ead exta ifomatio equied though the AXI4-Lite Cotol ad Status Registe Respode iteface by eadig cofiguatio egiste of iteest.

Table 67.  Cotol Shadow Iteface—Available Settigs of Vaious Cofiguatio Registe Fields
Fuctio Desciptio
Bus Maste Eable
  • The applicatio logic equies the BME ifomatio to detemie if it ca geeate equest fo a paticula fuctio.
  • Each fuctio i the applicatio logic caot geeate bus maste equests uless its coespodig BME is set.
  • The applicatio logic moitos cotol shadow iteface fo BME evet fo this pupose.
  • Sice the GTS AXI Steamig IP does ot autoomously geeate bus maste equest by itself, it does ot qualify the tasmit path with BME settigs ad solely elies o applicatio.
MSI-X Mask
  • It is the Fuctio Mask bit, idicate that all of the vectos associated with the Fuctio ae masked whe set, egadless of thei pe-vecto Mask bit values.
  • Each vecto's Mask bit detemies whethe the vecto is masked o ot whe this bit is clea.
MSI-X Eable
  • The applicatio logic equies MSI-X Addess ad MSI-X Data ifomatio fom MSI-X capability to geeate the MSI-X iteupt.
  • The applicatio logic moitos cotol shadow iteface fo MSI-X Eable evet to ead these additioal ifomatio fom MSI-X capability.
MemSpace Eable
  • It cotols a Fuctio's espose to Memoy Space accesses.
  • Whe this bit is Clea, all eceived Memoy Space accesses ae caused to be hadled as Usuppoted Requests.
  • Whe this bit is set, the Fuctio is eabled to decode the addess ad futhe pocess Memoy Space accesses.
  • Fo a Fuctio with a Type 1 Cofiguatio Space heade, this bit cotols the espose to the Memoy Space accesses eceived o its Pimay Side.
ExpRom Eable It idicates whethe o ot the Fuctio accepts accesses to its expasio ROM. Whe this bit is 0b, the Fuctio's expasio ROM addess space is disabled. Whe the bit is 1b, the addess decodig is eabled usig the paametes i the othe pat of the Expasio ROM Base Addess egiste.
TPH Req Eable
  • The fuctio suppots all opeatioal modes of TPH, o ST mode, iteupt vecto mode o device specific mode.
  • The HOST commuicates mode of opeatio by witig ST Mode Select bits i TPH equeste cotol egiste.
  • The applicatio eads this egiste ad geeates taffic oly whe TPH equeste eable bit is set.
ATS Eable
  • The fuctio ca ead Smallest Taslatio Uit (STU) field fom ATS cotol egiste whe ATS eable bit is set.
  • The followig figue shows output o the Cotol Shadow iteface whe thee is a update to the cotol shadow bits i the HIP cofiguatio egiste.
MSI Eable
  • The applicatio logic equies MSI Addess ad MSI Data ifomatio fom MSI capability to geeate MSI iteupt.
  • The applicatio logic moitos cotol shadow iteface fo MSI Eable evet to ead this additioal ifomatio fom MSI capability.
MSI Mask It idicates the Fuctio suppots MSI Pe-Vecto Maskig whe set ad ot suppoted whe clea.
Exteded Tag It idicates 8-bit Tag field geeatio is eabled whe set ad 5-bit Tag field geeatio whe clea.
10bit Tag Req Eable It idicates that the Requeste is pemitted to use 10-Bit Tags whe set, ot pemitted whe clea.
PTM Eable It idicates that a Fuctio is pemitted to paticipate i the PTM mechaism accodig to its selected oles whe set ad ot pemitted whe it is cleaed.
Maximum Payload Size (MPS)
The defied ecodigs ae:
  • 000b: 128 bytes max payload size
  • 001b: 256 bytes max payload size
  • 010b: 512 bytes max payload size
  • 011b: 1024 bytes max payload size
  • 100b: 2048 bytes max payload size
  • 101b: 4096 bytes max payload size
  • 110b: Reseved
  • 111b: Reseved
Maximum Read Request Size (MRRS)
The defied ecodigs ae:
  • 000b: 128 bytes maximum Read Request size
  • 001b: 256 bytes maximum Read Request size
  • 010b: 512 bytes maximum Read Request size
  • 011b: 1024 bytes maximum Read Request size
  • 100b: 2048 bytes maximum Read Request size
  • 101b: 4096 bytes maximum Read Request size
  • 110b: Reseved
  • 111b: Reseved
Vitual Fuctio (VF) Eable
  • The Vitual Fuctio i applicatio logic caot geeate ay taffic uless they ae eabled by HOST. The umbe of VFs eabled ca be diffeet tha the umbe of VFs advetised as iitial VFs.
  • The applicatio logic ca fid the umbe of VFs visible by eadig the NumVFs egiste i the SR-IOV capability.
  • The ead of this egiste must be tiggeed afte the VF Eable bit is set by HOST.
  • It idicates that VFs associated with PF ae accessible i the PCI Expess* fabic whe set.
  • VFs ae disabled ad ot visible i the PCI Expess* fabic whe clea.
Page Request Eable It idicates that the Page Request Iteface is allowed to make page equests whe set, ot allowed whe clea.

The followig figue shows the output o the cotol shadow iteface whe thee is a update to the cotol shadow bits i the HIP cofiguatio egiste.

Figue 54. Cotol Shadow Iteface Timig Diagam Duig a Update
Table 68.  Cotol Shadow Iteface Sigals = 0 o 1, p0 = pot 0, ad p1 = pot 1
Note: Pot 1 is oly available i D-Seies FPGAs
Sigal Name Diectio Clock Domai Desciptio
p<>_ss_app_st_ctlshadow_tvalid Output p<>_axi_lite_clk

The GTS AXI Steamig IP assets this output fo oe clock cycle whe thee is a update to the egiste fields beig moitoed, because of a Cofiguatio Wite pefomed by the oot complex.

You ca copy the ew settigs of the egiste fields fom the p<>_ss_app_st_ctlshadow_tdata[39:0] bus.

p<>_ss_app_st_ctlshadow_tdata[39:0] Output p<>_axi_lite_clk

Whe p<>_ss_app_st_ctlshadow_tvalid has bee asseted, this output povides the cuet settigs of the egiste fields of the associated Fuctio.

  • Bit [2:0]: Idetifies the physical fuctio umbe of cofiguatio egiste.
  • Bit [13:3]: Idetifies the vitual fuctio umbe of cofiguatio egiste.
  • Bit [14]: Idicates ifomatio is fo vitual fuctio implemeted i slot's physical fuctio.
  • Bit [19:15]: Idetifies the slot umbe of cofiguatio egiste.
  • Bit [20]: Bus Maste Eable
  • Bit [21]: MSI-X Mask
  • Bit [22]: MSI-X Eable
  • Bit [23]: MemSpace Eable
  • Bit [24]: ExpRom Eable
  • Bit [25]: TPH Req Eable
  • Bit [26]: ATS Eable
  • Bit [27]: MSI Eable
  • Bit [28]: MSI Mask
  • Bit [29]: Exteded Tag
  • Bit [30]: 10Bit Tag Req Eable
  • Bit [31]: PTM Eable
  • Bit [34:32]: MPS
  • Bit [37:35]: MRRS
  • Bit [38]: VF Eable
  • Bit [39]: Page Request Eable
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