GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

4.2. Resets

The GTS AXI Steamig IP has two types of esets:

  • Bus Resets—The bus esets ae AXI specificatio defied eset sigals, that is used to eset the logic i the GTS AXI Steamig IP itefacig with AXI fabic.
  • IP Resets—The IP eset sigals pefom cold/wam eset sequeces.
The GTS AXI Steamig IP has the followig eset domais to dive the vaious itefaces.
Table 10.  Reset Domais i the GTS AXI Steamig IP
Reset Domai Type Desciptio
Cold eset IP eset

A Fudametal Reset followig the applicatio of mai powe.

Iitiated by the deassetio of pi_pest_ sigal. This esets the followig:
  • Bus esets (AXI-Steam/AXI-Lite)
  • Had IP
  • Sticky egistes of cofiguatio space

Whe cold eset is tiggeed, wam eset ad bus esets must be asseted.

Refe to PCI Expess* Base Specificatio Revisio 4.0 fo moe details o cold eset.

Wam eset IP eset
A Fudametal Reset without cyclig mai powe. This esets the followig:
  • Bus esets (AXI-Steam/AXI-Lite)
  • Had IP

The wam eset ca be tiggeed multiple times by use without goig though cold eset sequece. Whe wam eset is tiggeed, Bus esets must be asseted.

Refe to the PCI Expess* Base Specificatio Revisio 4.0 fo moe details o wam eset.

AXI-Steam eset Bus eset This esets the AXI-Steam mai data path iteface (e.g., AXI-Steam TX/RX).
AXI-Lite eset Bus eset This esets the AXI4-Lite Cotol ad Status Registe Respode iteface (e.g., Completio timeout, cotol ad status egiste).

Fo each GTS bak, thee ae two pis i HVIO baks with optioal fuctio as platfom PCIe* eset (PERST#) fo the PCIe* lik i the bak. You ca coect PERST# to eithe oe of the eset pis. Assig pi_pest iput pot of the GTS AXI Steamig IP to the locatio of the eset pi coected to PERST#. Fo the eset pi ot used fo PERST#, it ca be used as a geeic HVIO sigal. Fo example, if the PIN_PERST_N_CVP_L1A_0 pi i Bak 5A is coected to PERST# fo the PCIe* lik i Bak L1A, the PIN_PERST_N_CVP_L1A_1 pi i Bak 5B ca be used as a geeic HVIO sigal. Resettig a PCIe* lik i oe bak does ot affect the PCIe* liks i othe baks.

Fo a desciptio of the dual-pupose pis i the HVIO baks fuctio as PCIe* platfom eset, efe to the Pi Coectio Guidelies: Agilex™ 5 FPGAs ad SoCs .
Note: Fo Agilex™ 5 ES E-Seies devices i the cuet Quatus® Pime softwae elease, you must assig both p0_pi_pest__i ad p0_pi_pest__1_i pots to the locatio of the eset pis i HVIO baks as show i the followig table. Coect PERST# to eithe oe of the eset pis. Fo the othe eset pi that is ot used as PERST#, it must be left floatig at boad level. Fo example, fo a PCIe* lik i GTS bak L1A, assig p0_pi_pest__i to pi PIN_PERST_N_CVP_L1A_0 ad assig p0_pi_pest__1_i to pi PIN_PERST_N_CVP_L1A_1. If you coect PERST# to PIN_PERST_N_CVP_L1A_0, leave PIN_PERST_N_CVP_L1A_1 floatig at boad level.
Table 11.  Pi Locatio Assigmet fo p0_pi_pest__i ad p0_pi_pest__1_i Pots
PCIe* Lik i GTS Bak HVIO Reset Pis Divig pi_pest Pot
p0_pi_pest__i p0_pi_pest__i
Bak L1A PIN_PERST_N_CVP_L1A_0 PIN_PERST_N_CVP_L1A_1
Bak L1B PIN_PERST_N_CVP_L1B_0 PIN_PERST_N_CVP_L1B_1
Bak L1C PIN_PERST_N_CVP_L1C_0 PIN_PERST_N_CVP_L1C_1
Bak R4A PIN_PERST_N_R4A_1 PIN_PERST_N_R4A_0
Bak R4B PIN_PERST_N_R4B_1 PIN_PERST_N_R4B_0
Bak R4C PIN_PERST_N_R4C_1 PIN_PERST_N_R4C_0

Avoid tiggeig pi_pest_ duig a Fuctioal Level Reset o befoe a Fuctioal Level Reset completio. The miimum iteval equiemet betwee two cosecutive eset is 500 μs. It is applicable to PERST# ad hot eset. I the othe wods, the miimum iteval time equied betwee the deassetio of the PERST# to the assetio of the ext PERST# is 500 μs.

Figue 11. Reset Domais
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