GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

Download PDF
ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals Cold Reset Ety ad Exit Sequece Wam Reset Ety ad Exit Sequece Use Reset Sequece Iitiated Cold Reset Ety ad Exit Sequece Use Reset Sequece Iitiated Wam Reset Ety ad Exit Sequece
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

6.2.2. Interface Reset Signals

Table 58.  Iteface Reset Sigals = 0 o 1, p0 = pot 0, ad p1 = pot 1
Note: Pot 1 is oly available i D-Seies FPGAs
EP = Edpoit, RP = Root Pot, BP = TLP Bypass
Sigal Name Diectio Pot Mode Desciptio
p<>_subsystem_cold_st_ Iput EP/RP/BP

GTS AXI Steamig IP global eset.

Active low sigal. Resets sticky egiste bits.

Ca be implemeted as sychoous o asychoous eset.

p<>_subsystem_wam_st_

Iput EP/RP/BP

GTS AXI Steamig IP wam eset.

Active low sigal. Does ot eset sticky egiste bits.

Ca be implemeted as sychoous o asychoous eset.
p<>_subsystem_cold_st_ack_ Output EP/RP/BP

Idicates that a cold eset actio is completed by the GTS AXI Steamig IP.

Asychoous hadshake sigal
p<>_subsystem_wam_st_ack_ Output EP/RP/BP

Idicates that a wam eset actio is completed by the GTS AXI Steamig IP.

Asychoous hadshake sigal.
p<>_axi_st_aeset_ Iput EP/RP/BP

Used to eset the AXI-Steam datapath iteface. Active low eset sigal.

The eset sigal ca be asseted asychoously, but deassetio must be sychoous afte the isig edge of p<>_axi_st_clk.

p<>_axi_lite_aeset_ Iput EP/RP/BP

. Used to eset the AXI4-Lite Cotol ad Status Registe Respode iteface. Active low eset sigal.

The eset sigal ca be asseted asychoously, but deassetio must be sychoous afte the isig edge of p<>_axi_lite_clk.

p<>_subsystem_st_eq Iput EP/RP/BP

Reset ety idicatio fom use eset cotol logic.

The GTS AXI Steamig IP queies the blocks i desig upo eceivig this equest ad seds a ackowledgmet back whe the block is eady fo eset ety.

Asychoous hadshake sigal.
p<>_subsystem_st_dy Output EP/RP/BP

Ready sigal fo the eset ety idicatio fom the GTS AXI Steamig IP to the use eset cotol logic.

Asychoous hadshake sigal.
p<>_iitiate_wamst_eq Output EP/RP/BP

Wam Reset ety equied idicatio fom the IP coe to use eset cotol logic.

The iitiato block caot issue ew eset ety equest util pevious eset sequece (etie eset opeatio) is completed.

Asychoous hadshake sigal.
p<>_iitiate_st_eq_dy Iput EP/RP/BP

Idicates use eset cotol logic has accepted iitiatio equest ad stats issuig esets.

Asychoous hadshake sigal.
p0_pi_pest__i

p0_pi_pest__1_i

p1_pi_pest__i

Iput EP/RP/BP

This is a active low iput fo the PERST# fuctio defied by the PCIe* specificatio. Coect PERST# to eithe oe of the eset pis.

You must assig a weak pull dow to this pi i the Quatus® Pime softwae settig file. Example:

set_istace_assigmet -ame WEAK_PULL_DOWN ON -to p0_pi_pest__i
p<>_pi_pest_ Output EP/RP/BP This is the PERST# idicatio fo the HIP.
p<>_eset_status_ Output EP/RP/BP

Active low sigal. Whe low, it idicates the HIP is i eset state.

The applicatio logic ca use this sigal to dive its eset etwok.

Sychoous to coeclkout_hip of HIP.

iit_doe Iput EP/RP/BP

A "1" o this active low sigal idicates that the FPGA device is ot yet fully cofigued.

A "0" idicates the device has bee cofigued ad is i omal opeatig mode.
Note: You must implemet the use eset sequece i applicatio use logic ad follow the assetio ad deassetio sequece fo gaceful ety ad exit fo each of the esets (cold, wam, etc.).

The followig table idicates the sigals o blocks used fo each type of eset.

Table 59.  Sigals o Blocks Used fo Reset Type
Reset Type Sigals/Blocks Ude Reset
Cold Reset
  • subsystem_cold_st_ ad subsystem_wam_st_ ae asseted.
  • p0_axi_st_aeset_ ad p0_axi_lite_aeset_ ae asseted.
  • HIP udegoes eset.
Wam Reset (e.g., LTSSM Hot eset)
  • subsystem_wam_st_ is asseted.
  • p0_axi_st_aeset_ ad p0_axi_lite_aeset_ ae asseted.
  • HIP udegoes eset too.
The expected eset isolatio equiemets fo eset domai cossigs ae show i the followig table:
Table 60.  Reset Isolatio Requiemet fo Reset Domai Cossigs
  • No: No eset isolatio equied fo Colum->Row Reset Domai Cossig
  • Yes: Reset isolatio equied fo Colum->Row Reset Domai Cossig
  • N/A: Not applicable sice same Reset Domai Cossig
Colum: Souce

Row: Destiatio

 Cold Reset HIP Reset Wam Reset AXI-Steam Reset AXI-Lite Reset
Cold Reset N/A No Yes No No
HIP Reset No N/A No No No
Wam Reset No No N/A No No
AXI-Steam Reset No No No N/A No
AXI-Lite Reset No No No No N/A
Note: I edpoit mode, the wam eset ca be asseted without cold eset i sceaios such as LTSSM hot eset.

Cold Reset Ety ad Exit Sequece

Followig is the Cold Reset ety.
  1. Cold Reset is iitiated by the deassetio of HIP iput sigal p<>_pi_pest__i.
  2. HIP assets pld_lik_eset_eq to the GTS AXI Steamig IP.
  3. The GTS AXI Steamig IP otifies the use eset cotolle by assetig p<>_iitiate_wamst_eq.
  4. The use eset cotolle assets p0_subsystem_st_eq.
  5. The GTS AXI Steamig IP sequeces its iteal blocks fo eset ety. Whe the iteal blocks ae eady fo eset, the GTS AXI Steamig IP assets p<>_subsystem_st_dy to the use eset cotolle.
  6. The use eset cotolle ackowledges to the GTS AXI Steamig IP that it is eady fo eset by assetig p<>_iitiate_st_eq_dy.
  7. The GTS AXI Steamig IP the assets pld_wam_st_dy to HIP.
  8. HIP assets p<>_eset_status_ idicatig the applicatio logic eeds to be i eset.
  9. Use eset cotolle assets p<>_subsystem_cold_st_, p<>_subsystem_wam_st_, p<>_axi_st_aeset_, ad p<>_axi_lite_aeset_.
Figue 40. Cold Reset Ety ad Exit Sequece Timig Diagam

Wam Reset Ety ad Exit Sequece

Wam Reset is iitiated by the assetio of a HIP evet, fo example, hot eset. Followig is the Wam Reset ety sequece.
  1. HIP assets pld_lik_eset_eq to the GTS AXI Steamig IP.
  2. The GTS AXI Steamig IP otifies the use eset cotolle by assetig p<>_iitiate_wamst_eq.
  3. The use eset cotolle the assets p<>_subsystem_st_eq.
  4. The GTS AXI Steamig IP sequeces its iteal blocks fo eset ety. Whe the iteal blocks ae eady fo eset, the GTS AXI Steamig IP assets p<>_subsystem_st_dy to the use eset cotolle.
  5. The use eset cotolle ackowledges to the subsystem that it is eady fo eset by assetig p<>_iitiate_st_eq_dy.
  6. The GTS AXI Steamig IP the assets pld_wam_st_dy to HIP.
  7. HIP assets p<>_eset_status_ idicatig the applicatio logic eeds to be i eset.
  8. The use eset cotolle assets p<>_subsystem_wam_st_, p<>_axi_st_aeset_, ad p<>_axi_lite_aeset_.
Note: The Wam Reset flow is simila to Cold Reset flow, with the exceptio that p<>_pi_pest_ ad p<>_subsystem_cold_st_ ae ot asseted fo wam eset.
Figue 41. Wam Reset Ety ad Exit Sequece Timig Diagam

Use Reset Sequece Iitiated Cold Reset Ety ad Exit Sequece

  1. Cold Reset is iitiated by the use eset cotolle by the assetio of the p<>_subsystem_st_eq.
  2. The GTS AXI Steamig IP sequeces its iteal blocks fo eset ety. Whe the iteal blocks ae eady fo eset, the GTS AXI Steamig IP assets p<>_subsystem_st_dy to use eset cotolle.
  3. Use eset cotolle assets p<>_subsystem_cold_st_, p<>_subsystem_wam_st_, p<>_axi_st_aeset_, ad p<>_axi_lite_aeset_.
Figue 42. Use Reset Sequece Iitiated Cold Reset Ety ad Exit Sequece Timig Diagam

Use Reset Sequece Iitiated Wam Reset Ety ad Exit Sequece

Use eset cotolle tiggeed Wam Reset flow is the same as the use eset cotolle tiggeed Cold Reset flow, with the exceptio that the p<>_subsystem_cold_st_ is ot asseted fo this flow.

Figue 43. Use Reset Sequece Iitiated Wam Reset Ety ad Exit Sequece Timig Diagam
Level Two Title