GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

A.1.2. Debugging Data Transfer and Performance Issues

Thee ae may possible easos causig the PCIe* lik to stop tasmittig data. The PCI Expess* base specificatio defies thee types of eos, outlied i the table below:

Table 116.  Eo Types Defied by the PCI Expess* Base Specificatio
Type Resposible Aget Desciptio

Coectable

Hadwae While coectable eos may affect system pefomace, data itegity is maitaied.

Ucoectable, ofatal

 Device softwae

Ucoectable, o-fatal eos ae defied as eos i which data is lost, but system itegity is maitaied. Fo example, the fabic may lose a paticula TLP, but it still woks without poblems.

Ucoectable, fatal

System softwae Eos geeated by a loss of data ad system failue ae cosideed ucoectable ad fatal. Softwae must detemie how to hadle such eos: whethe to eset the lik o implemet othe meas to miimize the poblem.

Each PCI Expess* compliat device must implemet a basic level of eo maagemet ad ca optioally implemet advaced eo maagemet. The PCI Expess* Advaced Eo Repotig Capability is a optioal Exteded Capability that may be implemeted by PCI Expess* device fuctios suppotig advaced eo cotol ad epotig.

The GTS AXI Steamig IP implemets both basic ad advaced eo epotig. Eo hadlig fo a Root Pot is moe complex tha that of a Edpoit. I this IP, the Physical Fuctios (PFs) ae always capable of AER (eabled by default). Thee is o AER implemetatio fo Vitual Fuctios (VFs). Use the AER capability of the IP to idetify the type of eo ad the potocol stack laye i which the eo may have occued.

Refe to the PCI Expess* Capability Stuctues sectio of the Cofiguatio Space Registes appedix fo the AER Exteded Capability Stuctue ad the associated egistes.

Table 117.  Coectable Eo Status Registe (AER)
Obsevatio Issue Resolutio

Receive eo bit set

Physical laye eo which may be due to a PCS eo whe a lae is i L0, o a Cotol symbol beig eceived i the wog lae, o sigal Itegity issues whee the lik may tasitio fom L0 to the Recovey state.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Bad DLLP bit set

Data lik laye eo which may occu whe a CRC veificatio fails.

 Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Bad TLP bit set

Data lik laye eo which may occu whe a LCRC veificatio fails o whe a sequece umbe eo occus.

 Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Replay_um_ollove bit set

Data lik laye eo which may be due to TLPs set without success (o ACK) fou times i a ow.

 Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

eplay time timeout status bit set

Data lik laye eo which may occu whe o ACK o NAK was eceived withi the timeout peiod fo the TLPs tasmitted.

 Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Coected iteal eo bits set

Tasactio laye eo which may be due to a ECC eo i the iteal Had IP RAM.

 Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.
Table 118.  Ucoectable Eo Status Registe (AER)
Obsevatio Issue Resolutio

Data lik potocol eo

Data lik laye eo which may be due to tasmitte eceivig a ACK/NAK whose Seq ID does ot coespod to a uackowledged TLP o ACK sequece umbe.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Supise dow eo

Data lik laye eo which may be due to lik_up_o gettig deasseted duig L0, idicatig the physical laye lik is goig dow uexpectedly.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Flow cotol potocol eo

Tasactio laye eo which ca be due to the eceive epotig moe tha the allowed cedit limit. This eo occus whe a compoet does ot eceive updated flow cotol cedits with the 200 μs limit.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Poisoed TLP eceived

Tasactio laye eo which ca be due to a eceived TLP with the EP bit set.

 Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Completio timeout

Tasactio laye eo which ca be due to a completio ot eceived withi the equied amout of time afte a o-posted equest was set.

 Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Complete abot

Tasactio laye eo which ca be due to a complete beig uable to fulfill a equest due to a poblem with the equeste o a failue of the complete.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Uexpected completio

Tasactio laye eo which ca be due to a equeste eceivig a completio that does ot match ay equest awaitig a completio. The TLP is deleted by the Had IP ad ot peseted to the Applicatio Laye.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Receive oveflow

Tasactio laye eo which ca be due to a eceive eceivig moe TLPs tha the available eceive buffe space. The TLP is deleted by the Had IP ad ot peseted to the Applicatio Laye.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Malfomed TLP

Tasactio laye eo which ca be due to eos i the eceived TLP heade. The TLP is deleted by the Had IP ad ot peseted to the Applicatio Laye.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

ECRC eo

Tasactio laye eo which ca be due to a ECRC check failue at the eceive despite the fact that the TLP is ot malfomed ad the LCRC check is valid. The Had IP block hadles this TLP automatically. If the TLP is a o-posted equest, the Had IP block geeates a completio with a complete abot status. The TLP is deleted by the Had IP ad ot peseted to the Applicatio Laye.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Usuppoted equest

Tasactio laye eo which ca be due to the complete beig uable to fulfill the equest. The TLP is deleted i the Had IP block ad ot peseted to the Applicatio Laye. If the TLP is a o-posted equest, the Had IP block geeates a completio with Usuppoted Request status.

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

ACS violatio

Tasactio laye eo which ca be due to access cotol eo i the eceived posted o o-posted equest.

 Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Ucoectable iteal eo

Tasactio laye eo which ca be due to a iteal eo that caot be coected by the hadwae.

 Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

TLP pefix blocked

EP o RP oly

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.

Poisoed TLP egess blocked

EP o RP oly

Use the AXI4-Lite Cotol ad Status Registe Respode iteface to obtai moe ifomatio about the eo.
Related Ifomatio
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