GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

A.2.5. Using the Agilex™ 5 Link Inspector

The Lik Ispecto is foud ude the PCIe Lik Ispecto tab afte opeig the Debug Toolkit.

The Lik Ispecto is eabled by default whe the Eable Debug Toolkit is eabled.

Figue 80. View of the Lik Ispecto

Whe the Dump LTSSM Sequece to Text File butto is iitially clicked, a text file (ltssm_sequece_dump_p0.txt) with the LTSSM ifomatio is ceated i the locatio fom whee the System Cosole widow is opeed. Depedig o the PCIe topology, thee ca be up to fou text files. Subsequet LTSSM sequece dumps ae appeded to the espective files.

Note: If you ope System Cosole i a diectoy that is ot witable, the text file caot be geeated. To avoid this issue, ope System Cosole fom the Commad Pompt widow (o a Widows system) o chage the diectoy's pemissio settigs to witable.
Example LTSSM Sequece Dump 
         LTSSM State                     | Time (s) |  LTSSM State #
0x0      DETECT_QUIET                    | 5284883    |  0                   
0x1      DETECT_ACTIVE                   | 197        |  1                   
0x2      POLLING_ACTIVE                  | 25399190   |  2                   
0x5      PRE_DETECT_QUIET                | 1050       |  3                   
0x0      DETECT_QUIET                    | 640830     |  4                   
0x1      DETECT_ACTIVE                   | 297        |  5                   
0x2      POLLING_ACTIVE                  | 25307183   |  6                   
0x3      POLLING_COMPLIANCE              | 17897600   |  7                   
0x2      POLLING_ACTIVE                  | 65697      |  8                   
0x4      POLLING_CONFIG                  | 24558927   |  9                   
0x7      CONFIG_LINKWD_START             | 147        |  10                  
0x8      CONFIG_LINKWD_ACCEPT            | 893        |  11                  
0x9      CONFIG_LANENUM_WAIT             | 1827       |  12                  
0xa      CONFIG_LANENUM_ACCEPT           | 127        |  13                  
0xb      CONFIG_COMPLETE                 | 1097       |  14                  
0xc      CONFIG_IDLE                     | 1070       |  15                  
0x11     L0                              | 50         |  16                  
0xd      RECOVERY_LOCK                   | 487        |  17                  
0xf      RECOVERY_RCVRCFG                | 3137       |  18                  
0xe      RECOVERY_SPEED                  | 2627750    |  19                  
0xd      RECOVERY_LOCK                   | 40         |  20                  
0x20     RECOVERY_EQ0                    | 10485737   |  21                  
0x21     RECOVERY_EQ1                    | 257        |  22                  
0x22     RECOVERY_EQ2                    | 9357540    |  23                  
0x23     RECOVERY_EQ3                    | 12973550   |  24                  
0xd      RECOVERY_LOCK                   | 133        |  25                  
0xf      RECOVERY_RCVRCFG                | 453        |  26                  
0x10     RECOVERY_IDLE                   | 63         |  27                  
0x11     L0                              | 187        |  28                  
0xd      RECOVERY_LOCK                   | 790        |  29                  
0xf      RECOVERY_RCVRCFG                | 2323       |  30                  
0xe      RECOVERY_SPEED                  | 2235913    |  31                  
0xd      RECOVERY_LOCK                   | 40         |  32                  
0x20     RECOVERY_EQ0                    | 14500      |  33                  
0x21     RECOVERY_EQ1                    | 197187     |  34                  
0x22     RECOVERY_EQ2                    | 5052290    |  35                  
0x23     RECOVERY_EQ3                    | 8748963    |  36                  
0xd      RECOVERY_LOCK                   | 73         |  37                  
0xf      RECOVERY_RCVRCFG                | 243        |  38                  
0x10     RECOVERY_IDLE                   | 40         |  39                  
0x11     L0                              | -          |  Cuet             


The cuet LTSSM state is: L0

Each LTSSM moito has a FIFO stoig the time values ad captued LTSSM states. Whe you choose to dump out the LTSSM states, eads ae depedet o the FIFO elemets ad ca empty out the FIFO.

The Lik Ispecto oly wites to its FIFO if thee is a state tasitio. I cases whee the lik is stable i L0, thee is o wite ad hece o text file is dumped.

Whe you wat to dump the LTSSM sequece, a sigle ead of the FIFO status of the espective coe is pefomed. Depedig o the empty status ad how may eties ae i the FIFO, successive eads ae executed.

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