GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging B. PIPE Mode Simulation C. Implementation of Address Translation Services (ATS) in Endpoint Mode
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Power Management 4.11. Config Retry Status Enable 4.12. Hot-Plug 4.13. Configuration Space Extension 4.14. Page Request Service (EP only) 4.15. Precision Time Measurement (PTM) 4.16. Single Root I/O Virtualization (SR-IOV) 4.17. Transaction Layer Packet (TLP) Bypass Mode 4.18. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Scheme
4.16. Single Root I/O Virtualization (SR-IOV) x
4.16.1. SR-IOV Implementation
4.17. Transaction Layer Packet (TLP) Bypass Mode x
4.17.1. AXI-Lite Usage for TLP Bypass Mode 4.17.2. Configuration TLP 4.17.3. Transmit Interface 4.17.4. Receive Interface 4.17.5. Malformed TLP 4.17.6. ECRC
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Configuration Extension Bus (CEB) Interface 6.6. Control Shadow Interface 6.7. Transmit Flow Control Credit Interface 6.8. Completion Timeout Interface 6.9. Control and Status Register Responder Interface 6.10. Function Level Reset Interface 6.11. TLP Bypass Error Reporting Interface 6.12. Error Interface 6.13. VF Error Flag Interface 6.14. VIRTIO PCI* Configuration Access Interface 6.15. Precision Time Measurement (PTM) Interface 6.16. Serial Data Signals 6.17. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.5. Configuration Extension Bus (CEB) Interface x
6.5.1. Configuration Extension Bus Request Interface 6.5.2. Configuration Extension Bus Response Interface
6.10. Function Level Reset Interface x
6.10.1. Function Level Reset Received Interface 6.10.2. Function Level Reset Completion Interface
6.14. VIRTIO PCI* Configuration Access Interface x
6.14.1. VIRTIO PCI Configuration Access Request Interface 6.14.2. VIRTIO PCI Configuration Access Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space 7.7. Intel-Defined VSEC Capability Register
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF PCI Express* Capability Structure 7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF TLP Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF PCI Express* Capability Structure x
7.6.2.1. PCI Express* Capability List Register 7.6.2.2. PCI Express* Device Capabilities Register 7.6.2.3. PCI Express* Device Control and Status Register 7.6.2.4. Link Capabilities Register 7.6.2.5. Link Control and Status Register 7.6.2.6. PCI Express* Device Capabilities 2 Register 7.6.2.7. PCI Express* Device Control and Status 2 Register 7.6.2.8. Link Capabilities 2 Register 7.6.2.9. Link Control and Status 2 Register
7.6.3. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.3.1. MSI-X Control Register 7.6.3.2. MSI-X Table Offset Register 7.6.3.3. MSI-X Pending Bit Array Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF TLP Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
B. PIPE Mode Simulation
C. Implementation of Address Translation Services (ATS) in Endpoint Mode

2.1. Supported Features

The GTS AXI Steamig IP suppots the followig featues:

PCI Expess* Featues

  • Complete potocol stack icludig the Tasactio, Data Lik, ad Physical Layes implemeted as Had IP.
  • Suppoted cofiguatios ae listed i the table below:
    Table 1.  Cofiguatios Suppoted by the GTS AXI Steamig IP
    Pot Mode PCIe* 3.0/ PCIe* 4.0 x8 1 PCIe* 3.0/ PCIe* 4.0 x4 PCIe* 3.0/ PCIe* 4.0 x2 PCIe* 3.0/ PCIe* 4.0 x1
    Edpoit (EP) Yes Yes Yes Yes
    Root Pot (RP)
    Tasactio Laye Packet (TLP) Bypass Mode
    Note: PCIe* 1.0/ PCIe* 2.0 speeds ae suppoted though lik dow-taiig.
  • Sepaate Refeece Clock with Idepedet Spead Spectum Clockig (SRIS)
    • Sepaate Refeece Clock with No Spead Spectum Clockig (SRNS)
    • Commo efeece clock achitectue
  • Sigle Vitual Chael (VC)
  • Capability Registes:
    • Message Sigaled Iteupt (MSI)
    • Message Sigal Iteupt Exteded (MSI-X)
    • Advaced Eo Repotig (AER) (PF oly)
    • Powe Maagemet (ASPM, D0 ad D3 PCIe* powe states) (PF oly)
    • Alteative Routig ID (ARI)
    • Addess Taslatio Sevices (ATS)
    • Page Request Sevice (PRS)
    • TLP Pocessig Hits (TPH)
    • Access Cotol Sevices (ACS)
    • Latecy Toleace Repotig (LTR)
    • Pocess Addess Space ID (PASID)
    • Vedo Specific Capability
  • Suppots up to 512-byte maximum payload size (MPS)
  • Suppots up to 4096-byte (4 KB) maximum ead equest size (MRRS)
  • 32/64-bit BAR suppot (Pefetchable/No-Pefetchable)
  • Expasio ROM BAR suppot
  • 10 bit Tag Suppot as equeste (x8 cotolle oly)
  • Numbe of tags
    • x4 cotolle: 32, 64, 128, 256
    • x8 cotolle: 32, 64, 128, 256, 512
  • Mai data path paity potectio
  • ECRC geeatio ad checkig
  • MSI-X Table i the GTS AXI Steamig IP (up to 2048 vectos pe fuctio)
  • Suppots device seial umbe capability
  • Atomic opeatios (Fetch/Add/Swap/CAS)
  • Suppots elaxed odeig o eceive side
  • Suppot TLP Bypass mode
    • Suppots upsteam pot ad dowsteam pot
    • Suppots autoomous hip mode
    • No Cofiguatio-via-Potocol (CvP) iit/update suppot
  • Pecisio Time Measuemet (PTM)
  • Suppot fo scaled flow cotol cedits
  • PCIe* 4.0 etime awae PCIe* cotolle
  • Suppots lae magiig at eceive
  • Suppot lik equalizatio fo PCIe* 3.0 ad above speed
  • FPGA coe cofiguatio though PCIe* lik (CvP iit)
  • FPGA coe cofiguatio update though PCIe* lik (CvP update)
  • Suppots lae evesal ad polaity ivesio
  • Hot-Plug (Root Pot mode oly)
  • Suppots autoomous Had IP mode—This mode allows the PCIe* Had IP to commuicate with the Host befoe the FPGA cofiguatio ad ety ito Use mode ae complete.
    Note: Uless Readiess Notificatios mechaisms ae used, the Root Complex o system softwae must allow at least 1.0 secod afte a Covetioal Reset of a device befoe it may detemie that a device that fails to etu a Successful Completio status fo a valid Cofiguatio Request is a boke device. This peiod is idepedet of how quickly Lik taiig completes.
  • Povided to exted the cofiguatio capabilities beyod the PCI* / PCIe* capabilities ad implemet Custome Specific Capabilities.
  • Suppots Applicatio Eo Repotig: The GTS AXI Steamig IP implemets Applicatio Eo Repotig egistes. These egistes allow you to idicate vaious eos. The GTS AXI Steamig IP logic the fowads this eo ifomatio to Had IP block (UR/CA/Completio Timeout/Poiso).
  • Tasactio odeig, deadlock avoidace.
    Note: You must implemet tasactio odeig i use applicatio logic.
  • Debug Toolkit fo egiste accesses ad debug (optioal).
  • The Quatus® Pime geeated desig examples.

Multi-fuctio ad Vitualizatio Featues (Optioal)

  • Sigle Root I/O Vitualizatio (SR-IOV) suppot (maximum 4 PFs, 256 VFs)
  • Suppots sigle TLP pefix pe TLP
  • Suppots VitIO PCI* Cofiguatio Registes
  • Scalable IOV
  • Fuctio Level Reset (FLR)

Use Iteface Featues

  • AXI4-Steam Tasmit (TX) iteface
    • The AXI4-Steam TX iteface compises the pimay sigals, ad povides the stat of the tasactio
    • Sigle Steam iteface
  • AXI4-Steam Receive (RX) iteface
    • The AXI4-Steam RX iteface compises the secoday sigals, ad povides the espose to the tasactio fom the TX
    • Suppot fo basic bae metal mode (fo example, sigle physical fuctio, AER, ad othes) ad vitualizatio mode (fo example, multiple physical fuctios, fuctio level eset, ad othes)
  • AXI4-Steam Badwidth
    • Scalable fequecy.
    • The opeatig fequecy selectio optios of 200, 250, 300, o 350 MHz.
  • Cotol ad Status Respode Iteface
    • This is the AXI4-Lite Cotol ad Status Iteface to access egistes implemeted i the GTS AXI Steamig IP modules, icludig PCI* / PCIe* Cofiguatio Registes of all Fuctios.
    • 32-bit data width at 100–250 MHz.
  • Cofiguatio Itecept iteface
    • The Cofiguatio Itecept Iteface (CII) allows the applicatio logic to detect the occuece of a Cofiguatio (CFG) equest o the lik ad to modify its behavio.
  • Suppots Lik Pate Cedits is exposed though the Tasmit Flow Cotol Cedit iteface. The cedits ae advetised as limit value specified i the PCIe* specificatio. You must check the availability of cedits fo tasmittig the TLP. The Receive side opeates o the AXI-Steam eady-valid hadshake.
  • Cotol Shadow Iteface povided to shadow the cotol ifomatio fom the cotol/commad egistes (Optioal).
  • Completio timeout iteface (Optioal)—The GTS AXI Steamig IP ca optioally tack outgoig o-posted packets to epot the completio timeout ifomatio to the applicatio.
1
Note: PCIe* x8 lik width is oly suppoted i Agilex™ 5 D-Seies FPGAs.
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