GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

4.1. Clocking

The GTS AXI Streaming IP has the following clock domains to drive the various interfaces. All the clocks must be always on for the correct functioning of a design.

Table 9.  Clock Domains in GTS AXI Streaming IP
Clock Domain Description
core_clk

This clock is synchronous to the PMA parallel clock. The frequency of this clock switches dynamically based on the negotiated link speed.

  • PCIe* 4.0: 1000 MHz
  • PCIe* 3.0: 500 MHz
  • PCIe* 2.0: 250 MHz
  • PCIe* 1.0: 125 MHz
pld_clk

This clock is generated from a System PLL located in the same GTS transceiver bank with PCIe* lanes. The System PLL IP is required in a GTS AXI Streaming design to generate the PLD clock. The clock frequency is statically set in the System PLL IP, and it must match the frequency in the GTS AXI Streaming IP.

  • PCIe* 4.0: 500/450/400/350/300/250/200 MHz (x8)
  • PCIe* 4.0: 350/300/250/200 MHz (x4)
  • PCIe* 4.0: 300/250/200 MHz (x2, x1)
  • PCIe* 3.0: 350/300/250/200 (x8)
  • PCIe* 3.0: 300/250/200 MHz (x4, x2, x1)
  • PCIe* 2.0/ PCIe* 1.0: PCIe* 2.0/ PCIe* 1.0 is supported only through the link down-training and not natively. Hence, the coreclkout_hip_toapp clock frequency depends on the configuration you choose in the IP parameter editor. For example, if you choose a PCIe* 3.0 x4 configuration, the application clock frequency is 300 MHz.
    Note: Refer to the Recommended FPGA Fabric Speed Grades section for selection guidance.
coreclkout_hip_toapp

The coreclkout_hip output of the HIP drives this clock. It has the same frequency as the pld_clk. Use this clock to drive application logic.

p0_axi_st_clk

This global clock signal is an input to the IP. This clock is used to clock the AXI-Stream Datapath interfaces (TX and RX) to the application logic. All signals of the AXI-Stream Datapath interface are sampled on the rising edge of p0_axi_st_clk. The p0_axi_st_clk port must be driven by coreclkout_hip_toapp.

p0_axi_lite_clk

This global clock signal is an input to the IP. This clock is used to clock the sideband interfaces, for example, control and status register interface, completion timeout interface, etc. All signals are sampled on the rising edge of p0_axi_lite_clk.

Frequency: 250 MHz

The p0_axi_lite_clk frequency is capped by speed grade:
  • 250 MHz for 4S
  • 200 MHz for 5S
  • 150 MHz for 6S

The following figure shows the clock domains in the GTS AXI Streaming IP. All the clocks must be always on for the correct functioning of a design.

Figure 9. Clock Domains in GTS AXI Streaming IP