Visible to Intel only — GUID: xtl1696475397170
Ixiasoft
Visible to Intel only — GUID: xtl1696475397170
Ixiasoft
4.1. Clocking
The GTS AXI Streaming IP has the following clock domains to drive the various interfaces. All the clocks must be always on for the correct functioning of a design.
Clock Domain | Description |
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core_clk | This clock is synchronous to the PMA parallel clock. The frequency of this clock switches dynamically based on the negotiated link speed.
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pld_clk | This clock is generated from a System PLL located in the same GTS transceiver bank with PCIe* lanes. The System PLL IP is required in a GTS AXI Streaming design to generate the PLD clock. The clock frequency is statically set in the System PLL IP, and it must match the frequency in the GTS AXI Streaming IP.
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coreclkout_hip_toapp | The coreclkout_hip output of the HIP drives this clock. It has the same frequency as the pld_clk. Use this clock to drive application logic. |
p0_axi_st_clk | This global clock signal is an input to the IP. This clock is used to clock the AXI-Stream Datapath interfaces (TX and RX) to the application logic. All signals of the AXI-Stream Datapath interface are sampled on the rising edge of p0_axi_st_clk. The p0_axi_st_clk port must be driven by coreclkout_hip_toapp. |
p0_axi_lite_clk | This global clock signal is an input to the IP. This clock is used to clock the sideband interfaces, for example, control and status register interface, completion timeout interface, etc. All signals are sampled on the rising edge of p0_axi_lite_clk. Frequency: 250 MHz
The p0_axi_lite_clk frequency is capped by speed grade:
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The following figure shows the clock domains in the GTS AXI Streaming IP. All the clocks must be always on for the correct functioning of a design.