GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

4.1.1. Reference Clock

There is one local and one regional reference clock pin in each GTS bank to drive the TX PLL and CDR in PMA, and the System PLL in the bank. For x4 mode, the TX PLL, CDR and System PLL can be driven from either the local or the regional reference clock pin in the same GTS bank, or driven from other banks through the regional reference clock networks. For x8 mode, the System PLL must be driven from the local reference clock pin of the GTS bank where the x8 controller is located; the TX PLL and CDR are driven from the regional reference clock pin in the same bank or other banks.

The reference clock to the System PLL must be available and stable before device configuration starts. Derive the reference clock from an independent and free-running local clock source. Alternatively, if the reference clock from the PCIe* link is available before device configuration starts, you can use it to drive the System PLL. Once the reference clock from the PCIe* link is active, it is not allowed to go down.

The following figure shows the reference clock to drive the System PLL is from an independent local oscillator. It does not share the reference clock from the PCIe* link which drives the TX PLL and CDR in PMA. The reference clock from the PCIe* link may not be available before device configuration starts.

Figure 10. System PLL Reference Clock from a Free Running Oscillator
Note: Refer to the Clock Architecture section in the GTS Transceiver PHY User Guide .