GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

8.2.2. PCI Express* Capability Structures

The layouts of the most basic capability structures are provided below. Refer to the PCI Express* Base Specification for more information about these registers.

Figure 64. Power Management Capability Structure—Byte Address Offsets and Layout
Figure 65. MSI Capability Structure
Figure 66.  PCI Express* Capability Structure—Byte Address Offsets and Layout
Figure 67. MSI-X Capability Structure
Figure 68.  PCI Express* AER Extended Capability Structure

Refer to the Excel-based GTS AXI Streaming Intel FPGA IP for PCI Express* Register Map for the detailed descriptions of the registers.