GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 8/07/2024
Public
Document Table of Contents

1. Introduction

Updated for:
Intel® Quartus® Prime Design Suite 24.2
IP Version 5.0.0

The GTS AXI Streaming Intel® FPGA IP for PCI Express* allows you to implement PCI Express* ( PCIe* ) in your design using Intel’s technology leading PCIe* hardened protocol stack in the Agilex™ 5 FPGA product family.

The monolithic GTS transceivers in the Agilex™ 5 FPGAs and SoCs are equipped with the PCIe* Hard IP that includes transaction, data link and physical layers and includes optional blocks, such as Single Root I/O Virtualization (SR-IOV) for applications requiring high bandwidth data transfer to and from the host memory and virtualization.

Attention: Any mention of GTS AXI Streaming IP in this document shall constitute a reference to the GTS AXI Streaming Intel® FPGA IP for PCI Express* .